Sigma DSP Audio Output Stops

Dear Team.

I am trying to interface my ADAU1452 REV BZ board with another SHARC hardware as shown below:

These are the settings in Sigma STudio .

Issue occurs once I connect the GND or SDATAOUT0 pin to the corresponding SHARC pin AUdio Output stops . So i played with the settings and found that a noisy Audio Output is observed when BCLK polarity was changed . Can you explain what am i missing in correctly interfacing the two hardware. Assume my SHARC hardware has no MCLK of its own (disabled) and all other clock settings in SHARC accepts the standard Sigma STudio clock formats such as LRCL 50/50 polarity negative and data I2S BCLK delay by 1

Regards,

Hermione.

Audio Signal Processors

adau1452

Audio Products

hardware

ADAU1452 REV BZ

V4.5

SigmaDSP Audio Processors

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