i2s delay chain from input to output
Hi, in these days I'm testing the ADAU 1761 codec connected in I2S with an FPGA that generates the stimulus signals in order to check the behaviour of ADAU.
The FPGA genearate a I2S toward the ADAU working at 8kHz with 256 bit for sample in TDM8 mode.
That what I see is that the sample in input (DAC) takes 4 samples to be forwarded in the output on the I2S output data (ADC).
how is possible that the process take 4 sample delay to forward a sample in input, is it possible that I'm making some setup errors.
At this step I'm using the SigmaStudio Version 4.7
Thank you for your attention and the help you are able to provide.
Greetings
Luca
Audio Signal Processors
Audio Products
hardware
ADAU1761 delay I2s forward data
SigmaDSP Audio Processors
adau1761
Show More
Hello Luca,
I2S is a stereo standard and TDM is multiple channel standard and you are using TDM8 for eight channels transmitted per sample period. Either way, all the channels are transmitted in one sample period.
So here is the breakdown of the data transfers.
1 sample period to transmit the samples from the FPGA to the DSP.
1 sample period is used internally to transfer the serial port shift register to internal memory location that holds the new sample.
1 sample period to calculate your ENTIRE program shown in the SigmaStudio schematic. It does not matter how complex, the entire program is executed in one sample period. (I should add here that if your program is too long then it will spill into the next sample period and run at half the sample rate. This is for the ADAU1761 processor only. the others have different behaviors if the program is too long) In your example the program takes the input sample from the memory location for the new sample and transfers it to the memory location used to send data to the serial output port.
1 sample to transmit the output sample out of the serial port.
There is your four sample delay. You seem surprised? What is your expectation?
Dave T
hello Dave
thanks for your kind answer but I did the same test increasing the coreclock frequency to 1024xFs and the result is one sample better.
Onestly at this frequency I expetc somthing better like 2 sample at worst.since the data do nothing more than a pipe from input to output
Any way thanks for the helpfull answer.
Kind regard
Luca
Hello Luca,
Three is the absolute minimum. How can it be any shorter? You have to shift the data in and out. This does not matter what part you use, that will take two sample periods. If I want to go answer my doorbell it will take me the time to walk across the room to get to the door. No way to avoid that. It takes one sample period to shift data from one part to another. Then you have to run the program during one sample period. How can this be done faster? We are working on our time warp generator/time machine but I think it is a few years before we release it. (LOL)
Alessandrill said:
I did the same test increasing the coreclock frequency to 1024xFs and the result is one sample better.
This tells me you had the settings wrong between the serial port sample rates and the core clock.
Which part is the clock master?
There is a setting for the core start pulse so you can synchronize to another clock source if you are using an external clock from the FPGA.
Give us the clocking details and supply your SigmaStudio project.
Dave T
Please log in to reply.