ADAU1701 ,sampling rate in complier and SR0,SR1 relation to i2s streaming rate
Thread Summary
The user encountered incorrect boost frequencies in a Dynamic Bass Boost experiment with the ADAU1701 in slave mode. The issue was caused by the core clock rate being too high when using 24.576 MHz and 12.288 MHz MCLKs. The solution is to set the PLL to 512xfs mode for 96 kHz sampling and 256xfs for 44.1 kHz, ensuring the core clock is around 50 MIPS. The SigmaStudio fs setting must match the actual sample rate, and changing the sample rate at runtime requires recompiling the program and updating the PLL configuration.AI Generated Content
Anyone can explain ,What happen with my system? or i doing wrong?
My experiment is have 2 streaming I2S 96Ks and 44.1 ks with my adau1701 slave mode that mean MKCI is 24.576 Mhz and 12.288 Mhz.
my adau1701 PLL_mode1 and PLL_mode0 is 10 that is 256xfs.
My sigma studio is test Dynamic Bass Boost set frequency=60 Hz. measure boost frequency by streaming pink noise 20-20khz and use spectrum analyzer measure result is shown
1. at 96k streaming ,complier sigma fs=96kHz, 2x (512 instruction),measure boost is 120Hz
2. at 96k streaming ,complier sigma fs=96kHz, 1x (1024 instruction),measure boost is 60Hz
3. at 96k streaming ,complier sigma fs=48kHz, 2x (512 instruction),measure boost is 240Hz
4. at 96k streaming ,complier sigma fs=48kHz, 1x (1024 instruction),measure boost is 120Hz
5. at 44.1k streaming ,complier sigma fs=96kHz, 2x (512 instruction),measure boost is 60Hz
6. at 44.1k streaming ,complier sigma fs=96kHz, 1x (1024 instruction),measure boost is 30Hz
7. at 44.1k streaming ,complier sigma fs=48kHz, 2x (512 instruction),measure boost is 120Hz
8. at 44.1k streaming ,complier sigma fs=48kHz, 1x (1024 instruction),measure boost is 60Hz
Audio Signal Processors
hardware
sample rate
i2s
sigmastudio
SigmaDSP Audio Processors
adau1701
Show More
Hello Taweewong,
There are a few things to unwrap here. Some of this I can blame the datasheet for not being explicit about the internal core frequency.
Let me start with the easiest and more obvious detail. The SigmaStudio fs setting MUST agree with the actual sample rate clocks that will be applied to the part. SigmaStudio has no way to know what the clocks actually are so it depends on you to tell it what clocks will be there. Then it will use that sample rate setting for things like calculating the filter coefficients and things timing related like time constants. If the setting does not agree then the corner frequencies will be wrong.
If you are actually sending it 44.1kHz clocks then you should be setting it to 44.1Khz not 48kHz. The difference is not that great so you did not really notice the difference in the corner frequency but you should set it for 44.1kHz.
For the PLL. You need to set it up so the core clock will have around 50MIPS. The internal circuits will not allow for faster times over all temperatures and silicon skews. Plus, power dissipation will be greater and digital timing internally will be a problem if the internal core frequency is too high. This is where the datasheet is not clear. this part is 50MIPS. Let us analyze the default mean values for a 48kHz sampling rate and a 12.288MHz MCLK input.
12.288MHz / 48k = 256. So you set the PLL to the 256x mode.
Internally, this PLL will multiply this MCLK by 4 to get the core clock of 49.152MHz.
49.152MHz / 48k = 1024. This is where the 1024 instructions comes from. One instruction per core clock cycle.
So when you put in 24MHz and still have it set to 256x the internal core clock rate is WAY too high. 98.304MHz.
If you want to run at 96kHz you have to set it to the 2x512 instructions. Because 49.152/48k= 512 instructions.
If you are putting in 24MHz then you need to set the PLL for 512 x fs mode. The numbers in the settings 64x,256x,384x and 512x are for the nominal 48kHz fs and the 1x (1024) setting.
Therefore, when you change to 96kHz you will have to stop the PLL and change the pin settings for the PLL and restart it. This is not easy to do and to take care of the little details like what are the settings when you power up? If you have a controller to do it then it has to take are of all of this.
This is enough for now. I am expecting some more questions from you.
Dave T
Thank you, Dave
that cause is OVER clock rate. PLL 512xfs is answer.
if its switch PLL mode BTW 2 clock 256xfs and 512xfs then change SR wit external MCU. then how i do with complier?
or u can advice to use fs complier?
Hello Taweewong,
fs in the compiler must be set to the actual sampling rate of the audio. If you change this during run time then it will be a problem because you have to recompile the program for this new sampling rate.
If your product has to change during run time then you will have to load in a new program as well as change the PLL configuration pins and the registers. Of course the registers will be loaded in with a new program.
Dave T
Please log in to reply.