ADAU1467 CLK Gen1 Bug?

Hello Jarrr,

It's not a bug. This is because your start pulse setting is still set for CG1's x 1 output, the start pulse register sets the DSP sample rate.

The CG1 outputs a 48KHz clock (because you set it as N/M=1/6), and then you set the start pulse as from CG1's x 1 output. which sets the DSP sample rate as 48KHz. So, now if you change the CG1 values, it will affect the core sample rate, which will affect the processing and the outputs.

I also noticed that you changed your serial output port 0 rate from CG2.

So the serial output port runs at 96KHz (CG2 is set for 96KHz, N/M=1/3). Now the serial port is picking up the same sample twice from the memory. You can see the mismatch here.

The core, serial port, software sample rate, converter rates everything should be synchronous in your system. Otherwise you will be either repeating or missing samples.

Have a look at this thread, it explains sigmaDSP sample rates.

Feel free to reach out if you need any further clarifications.

Regards,

Harish

Thanks a lot Harish! I have not noticed that start pulse is also clocked from CG1. I thought it is independent generator. Now it is clear.