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Q&A from Analog Devices EngineerZone: SigmaDSP/SigmaStudio and DSP discussions (34 topics).
34 topics · 141 messages
Filtered by: #clock ✕
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ADAU1462-150 PLL and other settings
Hi, I was starting implementation for the ADAU1462-150 and came accross some points that are unclear for me. 1) The datasheet shows in Table 20 on page 29 the predivider and feedback divider settings.
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ADAU1467 CLK Gen1 Bug?
Hi. I have found a bug. I need to know if you got the same result. Simple project: tone generator connected to the output. Output is clocked from Gen 2. Gen 1 not used. If I change gen 1 (which is not
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Clock sharing for multiple I2S SDATA Outputs
Hello, For a multichannel project I am using all 4 serial data output ports of an ADAU1466 DSP, each sending 2-Channel I2S (or potentially multichannel TDM) audio data to one of four DACs (expectig 3-
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SigmaStudio+ does not apply the “PLL Input Clock Divider” setting to the hex file, so it is not written to the EEPROM
Hello, I have again found a bug in SigmaStudio+2.3.0: SigmaStudio+ does not apply the “PLL Input Clock Divider” setting to the hex file, so it is not written to the EEPROM! Divide by 4” is always writ
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Serial interface clocking configuration help needed
I am looking for assistance on setting up the clocking of the output serial interface of ADAU1466. I'm using 24.576 MHz master clock fed to both ADAU1466 and 3pcs PCM1795 (connected to DSP via I2S int
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ADAU1701 Eval board development related.
Hi, After multiple failed attempts, I was finally able to successfully build ADAU1701 eval board. However while I was building the existing circuit I struggled a lot with VDRIVE and 1.8 voltage on pin
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ADAU1452 incoming I2S slave clocks routed to I2S slave output
Hello All, I have the ADAU1452 DSP being slave on one of the I2S inputs and on one of the I2S outputs. MCLK is fed by a crystal. Physically the master is connected to the BCLK/LRCLK/SDATA_IN0 and SDAT
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ADAU1452 slave/master I2S communication, clock routing
Dear All, I am working on a project where the ADAU1452 needs to receive I2S data from an MCU (MCU is master towards the DSP), from an ADC and a BT module (they are slaves towards the DSP). After recei
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ADAU1467 Jitter on CLKOUT and BCLK
Hey together, We have a problem with some jitter on CLKOUT pin as well as the BCLK pins on our ADAU1467. We supply our MCLK by a 24.576MHz oscillator. Please see the measurement of the 24.576MHz below
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ADAU1452 SDATA_OUT3 SLAVE to CLK DOMAIN 0 does not work
Hi, i have a project with an ADAU1452 where SDATA_OUT0 is configured with LRCLK and BCLK as Master. The signal is output on SDATA_OUT0. SDATA_OUT3 ist configured with LRCLK and BCLK as Slave to CLK do
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Problems with EVAL-ADAU1452RevBZ in TDM mode
Hi, I'm trying to develop a multi-canal system with ADAU1452 in TDM16 mode that communicates to ADAU1966A in Standalone Mode (TDM16, Slave serial audio interface and 256 × Fs ). I control the DS
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eval-adau1467 with external master clock - how?
I am trying to evaluate an external synth as master clock (si5340) for our dsp product based on adau1467. So, my idea was to connect the output from the synth to the middle pin on J3 on the adau-1467
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ADAU1452 Port Clock Speed Capability
Hi, In reference to the previous question as per the following link : https://ez.analog.com/dsp/sigmadsp/f/discussions/109083/adau1452-and-32bit-word-samples-with-filters-delay-and-volume-control---co
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ADAU1701 TDM In - I2S out
Hello, in my current project I'm using an ADAU1701. On my system MCU I implemented an USB-to-TDM-Interface which delivers 8 channels with 24 bits at 48 kHz via TDM8. The Masterclock is 24.576 MHz, the
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Digital Mic input clock domain on ADAU1452.
Hello everyone, I have a question about clock domain for digital mic input. I will use a distant microphone on a measurement system and wish to us a PDM Mic to optimise cable costs (2 pairs of "numeri
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Clock Routing
Hi ! I recently started designing an ADAU1466 based DSP board. After first considering the standard AD1938 as codec, i quickly diverted to separate ADC and DACs (Cirrus Logic in this case). Having res
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adau1446 input / output continuity
Hi, I have TDM2 16bit I2S selected on input 4 TD8 16bit I2S selected for output 4 on the adau1446. I'm switching clock domain 4 SD pin from input to output mode and switching the input/output on/off d
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ADAU1701 -- I2S source without MCLK
As I understand from the datasheet (for the ADA1701 mini evaluation board), when reading audio from an I²S source, I need to connect the MCLK (approx. 12MHz) to the ADAU1701 input. Is there a way arou
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ADAU1466 operating current and clock speed variation
Hello, and thanks in advance to the AD engineers who hopefully look at this! I would like to use the ADAU1466 in an upcoming design, but have a question about power consumption since my application is
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One quartz and one eeprom for two adau1701.
Hello everyone. I would need to use 2 ADAU1701 in the same project. The first use a sample rate at 96Khz the second at 48Khz. 2 questions: 1) you can derive the clock for the second ADAU from the firs
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Can I run ADAU1701 and AD1938 codec at different sample rates?
I have an ADAU1701 clocked by a 12.288MHz oscillator, which I am running at the 48kHz rate for the on-board DAC and ADC. I have a AD1938 codec with serial data pins connected to the ADAU1701. The AD19
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ADAU1452: using LRCLK_IN0 pin for both I2S input clock and Clock Generator 3 external FREF for I2S output clock
I searched for "ADAU1452 clock generator 3 input reference" and found no relavent discussion, hence this question. I am using ADAU1452. My design has two inputs: 1) ADC, which drives LRCLK_IN2 that is
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MCLK to ADAU1761 cannot be locked in Sigmastudio
Hi All I am developing a project for ADAU1761 . A active OSC =24.576MHz clock connect to MCLK pin. Now LINK and COMPILER , verify PLL status always keeps unlocking. checked the 24.576MHz clock by scop
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Wiring - Multiple DSP boards
Dear Sirs I've started a project to process 8 in x 16 out audio mono channels. Drawing on Sigma, I've found that I need 5 DSP's to do it. So I need some help on wiring and choose some parts of IC's (4
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impact on filter coeficient / auto switching 44.1-48 and MCLK
Hello, I couldnt find a conversation on this so here is the problem : how to configure sampling frequency in sigmastudio and what is impact on the filter coeficient when I2S input rate is changing ? w