Clock Routing

Hello again.

"Analog Devices product experts normally answer questions very quickly, sometimes within minutes of posting."

in regards to the above Analog Devices quote, i find it quite disappointing that no help or feedback is given at all.

Especially since i was redirected to this community after having contacted analog devices directly.

I can certainly understand your disappointment. Quick replies from ADI would be quite valuable.

I'll do my best, though I'm just another engineer.

In my experience, driving 3 chips with the clock, unbuffered, should be no problem, especially since they are nearby. And you can drive them all with one trace, really anywhere you want. 12.288MHz isn't really 'high speed' in most design situations. (Even 24MHz if you use that.)

I've also found 4 layer designs to be perfectly fine, if you want to reduce costs. With some care it's not hard to designate different areas for AVDD and DVDD.

Hello NNEU,

Sorry for the slow response. I have had several high priority projects recently and have not had the time to devote to the forum.

It is important to have a ground or power layer right next to the signal layers. This is where the electrostatic return currents will be travelling on so having only a partial plane on layer 5 is probably not the best.

If you go to a 4-layer board and combine the AVDD and DVDD as joe42 suggests, then take care to try to route the digital traces only over the DVDD part of the power plane. Crossing over between the AVDD and DVDD can cause some noise issues. Chances are they will not be bad enough to cause a problem but if it can be avoided it is a good idea. Any layout is always fraught with decisions and what is worse to do since trying to follow all the "rules" is usually not possible. I always try to thing of things like return signal currents, return currents from stray capacitance and then from electrostatic currents from the edges of the clocks. These last two are pretty much the same issues. So that usually helps me decide what to do.

For the clkout buffer question. If they are that close then I do not think you need a buffer. I would add a dampening resistor on the clckout signal to help reduce reflections. The pins on this part have adjustable drive strength and slew so they should have no problems driving three loads. Your question about how to run the signal is difficult to answer without seeing the actual PCB layout. If all the traces are fanned out from the CLKOUT pin and are of similar length then you will get three reflections back all at about the same time. This will probably cause a high over and under-shoot condition to exist. So there is an argument for a single trace with a branch off of the trace to go to the next part on the way to the furthest part. Then the reflections will be skewed in time.

Your question about drive capabilities. This is listed in Table 4 in the datasheet under the Digital Output section.

Dave T

Hi Dave, Hi Joe,

Thank you for both of your helpful answers !

It is important to have a ground or power layer right next to the signal layers. This is where the electrostatic return currents will be travelling on so having only a partial plane on layer 5 is probably not the best.

Expanding the plane to cover the entire board is not an issue. Actually - from what i understand - that would work quite nicely; if i route CLKOUT on the bottom layer, the trace would be right next to the DVDD plane.

I've also found 4 layer designs to be perfectly fine, if you want to reduce costs. With some care it's not hard to designate different areas for AVDD and DVDD.

Speaking of cost and performance; cost is not really an issue in this case. I'm aiming for maximum performance.

Another question in regards to this topic: I've seen a couple of Implementations with the ADAU1452 (so equally relevant to the ADAU), some practice extensive bypassing of each supply pin by the suggested 100nF ceramics and an additional 10uF electrolytic for each pin.

The evaluation boards data sheet suggests using one electrolytic per type of supply ( AVDD, DVDD, A_3V3 etc.)

Will extensive bypassing as described above improve performance ?

I will share a picture of the layout at a later stage, in the meantime i would be thankful for further clarification on the above questions.

Best regards,

Noel

Extensive bypassing is good practice but won't necessarily improve performance (maybe a bit on the analog power side). It more prevents glitches and things going wrong. It's not unusual to bypass power pins with 10nF, 100nF, and 1uF, then with 10uF elsewhere, to be really safe. A couple of extra small capacitors is trivial cost and board space.

I've finished a preliminary layout; i would appreciate any feedback or suggestions for improvements.

Thanks !

I didn't review it thoroughly but it looks OK from what I can see. I'd move your GND vias very close to the board though, rather than after the caps. I think some of the datasheets show layout suggestions.

Hi Joe,

Would you recommend a ground fill on the top and bottom layers ?

If yes, would one via per unconnected piece be sufficient of should i spread vias evenly on the planes ?

Best regards !

Ground fills are probably a good idea. Most designers scatter vias throughout to connect the planes but I'm not sure it matters all that much. There should be multiple connections though.