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Q&A from Analog Devices EngineerZone: SigmaDSP/SigmaStudio and DSP discussions (3 topics).
3 topics · 21 messages
Filtered by: #buffer ✕
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Fractional Delay Buffer Splitting Problem
When I create a project and use two fractional delay blocks that sample the same signal, the compiler shows that buffer space is reserved only once—which seems logical. I want to use 48 fractional del
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Clock Routing
Hi ! I recently started designing an ADAU1466 based DSP board. After first considering the standard AD1938 as codec, i quickly diverted to separate ADC and DACs (Cirrus Logic in this case). Having res
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Using TxBuffer_IC_1.dat for bootloading from a VB app (ADAU1761)
I am using VB because that's what I have the most experience in, and it was hard to find a lot of support for this part of my application. So I am sharing what I have come up with here. I am using a c