Can I run ADAU1701 and AD1938 codec at different sample rates?
I have an ADAU1701 clocked by a 12.288MHz oscillator, which I am running at the 48kHz rate for the on-board DAC and ADC. I have a AD1938 codec with serial data pins connected to the ADAU1701. The AD1938 DAC serial input is set to slave on the DSP's LRCLK, and the AD1938 ADC is set to master.
It looks like I can set the frequency of the DSP's OUTPUT_BCLK and OUTPUT_LRCLK to be, say, 96kHz, independent of the DSPs sample rate. Is this correct?
(The reason I'd like to do this is to minimize the AD1938 latency, which is reduced with higher sample rates)
Thanks,
John
Audio Signal Processors
sample rate
ad1938
Integrated/Special Purpose A/D Converters
clock
SigmaDSP Audio Processors
Audio CODECs
adau1701
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Hello Wygonski,
Yes, you can run the input and output serial ports at different rates but the problem is that there are no sample rate converters. So you really need to have everything running at the same rate. You can run the core faster but you lose instructions.
Have you considered using the ADAU1372 which is a low latency codec?
Dave T
Dave,
Thanks for your reply. I think I'm still unclear on this. So if I wanted to change the sample rate of the core, input, and output to 96kHz, then for the ADAU1701 I would 1) change the system sample rate on the toolbar to 96kHz, 2) change the Program Length to 2x(512 instructions). How should I change the LRCLK and BCLK frequency in the Serial Output Control Reg?
John
Hello John,
Yes, change the system sample rate on the toolbar to 96kHz and make sure to click "yes" when it asks to propagate the sampling rate to all cells. This is only for cells that use the sample rate for calculations. Like an oscillator cell or some filter cells. Most other cells this makes no difference.
Then correct, you change the program length to 512 instructions per frame.
The LRCLK and BCLK only need to be changed if the 1701 output port is a master. Then you set it for the 512 divisors. Because everything is based on the core clock rate of 49.152MHZ so dividing that down by 512 will give you 96kHZ.
The BCLK will depend on the data format of I2S or TDM. Then again, the divider settings are based on the core clock rate.
The input serial port is always a slave and will just follow what it being sent to it. If the output port is also set to a slave then it will also follow what is being sent to it. It needs to be correlated to the DSP sample rate and the master clock.
Dave T
Dave,
Thanks, that clears it up for me. I had been using this ADI FAQ for guidance, and since I am using the ADAU1701 output as master to the AD1938, I now know that I need to also change the settings in the serial output control reg as well.
Thanks also for the info on the low-latency sigma-delta codec--I'm married to the hardware at the moment, but maybe for the next hardware rev.
John
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