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Can the phase-locked loop of the ADAU1787 operate at 98.304 MHz? Can the speed of BCLK reach up to 49.152 MHz at its maximum?

SigmaDSP & SigmaStudio DrCai Aug 21, 2025 00:00 1 replies Original on forum ↗
Thread Summary

Thread Summary

The user encountered limitations with the ADAU1787 when trying to set BCLK to 49.152 MHz for 8-channel TDM at 192KHz. The final answer confirms that 24.576 MHz is the maximum BCLK speed. For 8-channel TDM at 192KHz, the user should use 16-bit per channel (8x16x192KHz = 24.576MHz).
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DrCai Question
Aug 21, 2025 00:00

Hi!

When I was using the ADAU1787, I employed the TDM mode of I2S and found that the maximum speed of BCLK was 24.576 MHz, and the sampling rate for 16 channels was 192K. However, my application scenario required an 8-channel TDM transmission at a sampling rate of 192K. Therefore, BCLK needed to be 49.152K. But SigmaStudio did not allow me to do this.

When I was using the ADAU1787, I employed the TDM mode of I2S and found that the maximum speed of BCLK was 24.576 MHz, and the sampling rate for 16 channels was 192K. However, my application scenario required an 8-channel TDM transmission at a sampling rate of 192K. Therefore, BCLK needed to be 49.152K. But SigmaStudio did not allow me to do this.

If it is not possible to do so, then could you please tell me what methods I can use to achieve a 49.152 MHz transmission for the output BCLK?

The control word of register SPT0_BCLK_SRC, I guess, is a coefficient control word for a PLL. When it is set to 100, it operates at 24.576 MHz. If it is set to 101, can it then work at 49.152 MHz?

Looking forward to your reply! Thank you very much! Wish you a good mood!

software

ADAU1787

sigmaStudio 4.7

Integrated/Special Purpose A/D Converters

sigmastudio

SigmaDSP Audio Processors

Audio CODECs

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Harishgowtham Reply
Aug 22, 2025 00:00

Hello DrCai,

Both of your questions seem to be breaching the datasheet's limitations.

Reg the PLL input frequency, according to the datasheet, its range must be between 30KHz to 27MHz.

The PLL output is between 32MHz to 50MHz.

Reg the BCLK, 24.576MHz is the maximum, you can't go over it and it doesn't guarantee that it will work as intended if you try to go above the maximum limits.

It is not a guarantee to work if you do anything which exceeds the limits given in the datasheet.

So, you can do TDM4 (32bit/ch) with 192KHz. (4x32x192KHz = 24.576MHz)

If you want TDM8, then use 16bit/ch. Now you can use TDM8 with 192KHz. (8x16x192KHz = 24.576MHz)

Let me know if you have any further questions.

Regards,

Harish

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