ADAU1761 PLL issues with MCLK 24.576mhz

Hi

If I set the PLL to Integer mode

Input DIV =1

PLL Integer =2

R2 PLLCRL = 0xXXXX XXXX 1001;

Thus MCLK 24.576 = Core Clock 49.152

The PLL will not lock

If I set the PLL to Integer mode

Input DIV =2

PLL Integer =4

R2 PLLCRL = 0xXXXX XXXX 2201;

Thus MCLK 24.576 = Core Clock 49.152

The PLL will lock, but on rare random occasions it will not

If I set the PLL to Integer mode

Input DIV =4

PLL Integer =8

R2 PLLCRL = 0xXXXX XXXX 4601;

Thus MCLK 24.576 = Core Clock 49.152

The PLL will lock , have not seen it fail yet, but time will tell

I am waiting 1 sec after powerup and 100ms after setting the PLLCTL before i start a loop of reading the Lock bit every 100ms for 10 secs.

So I am giving it every chance to lock

thoughts on this?

Audio Signal Processors

hardware

SigmaDSP Audio Processors

adau1761