How to phase shift two PCG CLK outputs?
Hello,
I cannot figure out how to setup two PCGs (e.g., PCG_A and PCG_B) to generate the following timings (TDM8 and I2S perfectly in phase):
This looks to be impossible to achieve even with the following settings:
// I2S
ClkConfig.bExternalTrigger=0;
ClkConfig.eClkInput=ADI_PCG_CLK_EXT;
ClkConfig.nDiv=8;
FsConfig.bExternalTrigger=0;
FsConfig.eClkInput=ADI_PCG_CLK_EXT;
FsConfig.eFsBypassMode=ADI_PCG_FSBYPASS_MODE_NORMAL;
FsConfig.nDiv=512;
FsConfig.nPhase=4+256;
FsConfig.nPulseWidth=256;
adi_pcg_Init(ADI_PCG_DEV_A,&ClkConfig,&FsConfig);
// TDM8
ClkConfig.bExternalTrigger=0;
ClkConfig.eClkInput=ADI_PCG_CLK_EXT;
ClkConfig.nDiv=2;
FsConfig.bExternalTrigger=0;
FsConfig.eClkInput=ADI_PCG_CLK_EXT;
FsConfig.eFsBypassMode=ADI_PCG_FSBYPASS_MODE_NORMAL;
FsConfig.nDiv=512;
FsConfig.nPhase=1;
FsConfig.nPulseWidth=256;
adi_pcg_Init(ADI_PCG_DEV_B,&ClkConfig,FsConfig);
leading to the following output waveforms:
in which, as you can see, the relative timings between FS and BCK of each respective audio bus is respected, but not the timing between the two FS signals nor the desired phase alignment between BCK edges (a falling edge in I2S BCK signal always corresponds to a rising edge in TDM BCK signal).
Since CLK outs of both PCG_A and PCG_B are always derived by dividing the same external clock source (OSC IC) it looks impossible to arbitrarily shift one BCK respectfully to another one (e.g., BCK falling edge of PCG_A will always occur during a rising edge of BCK outputted by PCG_B). The situation is even more complicated when trying to synchronize and relatively shift clocks generated by PCGs located in different DAI domains.
P.S.
I'm also able, obvs, to obtain the following result by setting I2S phase shift to 256 + 1 instead of 256 + 4, but the problem in the subject remains: I'm completely unable to shift BCK outputs, then I2S BCK rising/falling edges are always occurring during TDM8 BCK rising edges.
Edit Notes
Additional details provided.
[edited by: SpoonMan999 at 2:34 PM (GMT -5) on 10 Dec 2025]
Thread Notes
SpoonMan999 - Moved from ADSP-SC59x to Processors & DSP. Post date updated from Wednesday, December 10, 2025 11:55 AM UTC to Thursday, May 14, 2026 9:00 AM UTC to reflect the move.
SpoonMan999 - Moved from ADSP-SC59x to Processors & DSP. Post date updated from Thursday, May 14, 2026 9:00 AM UTC to Thursday, May 14, 2026 9:00 AM UTC to reflect the move.
ADSP-21569
Audio Signal Processors
software
i2s
21569
processors and dsp
adsp
clock
tdm
Processors and Microcontrollers
SHARC Audio Processors/SoCs
pcg
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Hi,
Yes, your understanding seems correct. While looking into the PCG registers, there is no option available to apply a phase shift to the generated clocks, only divider settings and a phase for Frame Sync are provided. Because of this, it may not be possible to introduce a timing shift between the BCK outputs of two different PCGs.
Regards,
Nandini C
Hi NandiniC and thanks for your answer, so you mean there's no chance to generate a TDM8 clock completely synchronous with another I2S clock????
It looks incredible that I cannot synchronize, for example, an SPDIF transmitter with an 8-channel DAC!
NandiniC bump!
Hi,
Yes, as mentioned earlier, there is no register option available to directly synchronize two PCGs.
However, could you please try using the PCG_SYNC_CLKx_I signal to synchronize the PCG. The PCG_SYNC1 and PCG_SYNC2 registers allow synchronization of the frame sync units with an external frame sync. For example, when the FSA_SYNC and FSB_SYNC bits in the PCG_SYNC1 register are enabled, Frame Sync A and Frame Sync B are synchronized to the external frame sync signal routed to PCG_SYNC_CLKx through the SRU.
Please refer the below links which might be helpful.
PCG synchronization
Problem with external sync for PCG
Also, could you try routing the output of one PCG to another PCG, along with the PCG_SYNC_CLKx signal and the external trigger option, and check whether this configuration meets your timing and synchronization requirements.
Regards,
Nandini C
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