Medium EQ frequency band control
Thread Summary
The user observed incorrect EQ behavior when using separate volume controls for left and right channels in a Sigma Studio design for the ADAU1761 eval board. The final answer suggests changing the core clock source from 'direct from MCLK' to 'PLL clock' to ensure sufficient MIPS per sample period, addressing potential issues due to reduced instruction cycles.AI Generated Content
Hi,
I'm using double precision second order medium EQ with 5 bands in my sigma studio design (For ADAU1761 eval board). It's input is fed from a shared volume control, having two channels. The issue that iIve observed is that the eq was working fine when a single shared volume control, with grow algorithm was used for my left and right inputs.
But when i separate the same design with two single volume sliders, the eq is not behaving properly. What I've observed is that for a 500Hz input audio, gain control was observed on 1KHz control of EQ. Similar case was observed for 1KHz input, where I was able to adjust the gain with 2KHz EQ. For the 5 bands, none of the inputs frequencies are not matching with input audio frequency when we try to control it. The only change in design was the splitting of single shared 2 channel volume control to two independent volume controls. I'm attaching the screenshots of my design for your reference.
This particular design above is the one that is working fine.
The test method i've followed is that i;ve fed frequency for each bands in EQ from an online frequency generator tool, through the Digital mic which are my source 0 and 1 in the design.
And the output was observed from the aux output for L and R in the ADAU eval board.
This the modified design where issue is observed.
Here I've removed the DC blocking filters for testing, the observation is same with or without them before the volume control.
Please let me know, if someone finds any missing configurations that would've led to this issue that I'm observing.
Thanks and appreciate your time.
software
processors and dsp
adau1761
EQ filter
Processors and Microcontrollers
Hello febin,
I will have a look at this volume control and filter related issue that you mentioned above.
I have also noticed that you used ''direct from MCLK'' as core clock source which bypasses the PLL. So, if your MCLK_IN is 12.288MHz then your core clock is also 12.288MHz which reduces the nominal core clock of 49.152MHz by 4. So, you will get 256 MIPS per sample period. 12.288MHz/48KHz = 256 instructions per sample period at 48KHz.
You have to use PLL to get the maximum core clock of 49.152MHz which gives 1024 instructions per sample period at 48KHz. So please change that clock source setting to 'PLL clock'.
Please change the setting like below and see if you can still observe the issue you mentioned. Because, when you grow the volume slider, it adds instruction. since you are running the core by 1/4 instructions, the issue would have happened due to lack of instruction cycles.
Please try this and get back.
Regards,
Harish
Hi Harishgowtham ,
Thanks for the quick and prompt response. The issue was indeed the lower number of instructions per clock.
I've updated the clock source and the EQ bands are functioning as expected !!
Really appreciate your time and consideration.
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