ADAU1451 Core sample rate settings

Hello.

I have a question regarding the sample rate setup of the ADAU1451 using SigmaStudio 3.14.

I am running my application on a custom board with a 24.576 MHz MCLK with all four I2S input data channels set as slave on the ADAU1451 and all four I2S output data channels as master, with a MCLK OUT enabled running at 12.288 MHz.

My aim is to have a system that converts everything at the input to a 96 kHz signal, which is then output on the I2S outputs. But I have experienced some issues with correctly setting the core rate to 96 kHz when following the specifications in the datasheets and the text under the SigmaStudios "Register Controls" tabs.

In "ROUTING MATRIX" I have set up my ASRCs to get the inputs from the four input channels (this has been verified to work correctly) and the output rates are set to "Use DSP core START_PULSE rate".

Under "CLOCK CONTROL" I have set the PLL CTRL 0 to "96" and PLL CTRL 1 to "Divide by 8" to achieve the 294.912 MHz system clock (PLL CLK SRC is set to "PLL clock").

Now, from here I assume that the Base_Fs is 48 kHz, as when I set the MCLK OUT setting to "Base_Fs x 256" I get my 12.288 MHz output as needed.

Furthermore I set the CLK GEN1 M to "3", and CLK GEN1 N to "1" to get an output of this clock generator to run at 96 kHz. This also works fine, as I am using this as my clock source for my I2S outputs, which follows the settings of this CLK GEN1 N and M values.

My problem/question occurs, when I go to the "CORE_CONTROL" tab. In here, I expected that the START_PULSE setting defines the core sample rate (and thereby also the target output rate of the ASRCs). This also seems to the case, but the definition says that it is set to multiples of Base_Fs.

Thus, since my Base_Fs must be 48 kHz (as verified with the MCLK OUT setting), I expected that I should set the START PULSE setting to "Base_Fs x 2 (96 kHz for 48 kHz base sample rate)".

But, when I do this, the output sounds strangely distorted and I can get strong aliasing at the output, when I test it with a 192 kHz source transmitting a 80 kHz sine wave (anything above 48 kHz gives aliasing at the output).

This indicates to me that the core rate at this point is actually running at 192 kHz and not 96 kHz!

If I then switch the START PULSE setting to "Base_Fs (96 kHz for 48 kHz base sample rate)", the aliasing disappears, and I can easily send a 40 kHz sine wave through the system, indicating that the system is actually running in 96 kHz.

So, my theory is that the START PULSE is actually set as multiple of the CLK GEN1 output rate and NOT the the Base_Fs.

I have done further testing to verify this, by e.g. setting the CLK GEN1 output rate to 48 kHz (by setting CLK GEN1 M to "6") there is still no aliasing and the output runs perfectly in 48 kHz.

Changing this does not alter the MCLK OUT rate, which still to me, again, verifies that the Base_Fs is 48 kHz.

So, to sum up:

The core sample rate is set by the START_PULSE setting, but it is defined as multiples of the CLK GEN1 output rate and NOT the Base_Fs as specified.

Is this something you can verify in any way?

I know that it is not a big deal, as I can get my system up and running perfectly and smooth in this way. But it has bugged me a lot to get to this point, as the specification (at least to me) is very confusing on this point.

So, hopefully this thread can also help others having the same issues, or maybe haven't recognized that their system is running at a double sample rate than the output clock, which causes a lot of audio artifacts.

Best regards, Jesper Thørring Jensen

Audio Signal Processors

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sample rate

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