Intermittent noise with ADAU1446 application

Hello,

Just a quick note to let you know I will be working on this soon.

Dave T

Hello,

I thought the schematic you attached was the SigmaStudio schematic. So I will comment on the hardware schematic and see where this goes.

IC3, the AD1939, The CM pin, pin 52, needs to be bypassed with a 100nf located close to the pins with the vias on the side away from the pins. Then a 47uf cap. You need both. This can cause noise issues.

What is IC4?

I don't fully understand what you are doing with the RROUT, RLOUT, FROUT, FLOUT. But I don't think this is the issue.

Can you look at the spectrum of the noise floor? This may give some clues as to where to look for the issue.

What is different with the DSP programs on the EEPROM and the programs you load up through SigmaStudio?

Dave T

Hi Dave

Appreciate your time on this. We've found that loading different Sigma Studio profiles can change the level of the noise, but because the noise occurs intermittently with any of the 'problem' profiles we don't believe the profile to be the cause of the noise. Just re-starting the amplifier can cause the noise-floor to shift between two levels - 'normal' or 'high', apparently at random.

So yes, we would much appreciate your feedback on the hardware schematic as we believe that's where the problem is.

We've run some more tests today looking at the digital data between the ADC and DSP. The character of the data appears to change between two states that correspond with the noise being present or not. We concluded from this that the noise may be coming from the ADC in the AD1939, so ran a further test to switch off the DSP inputs via Sigma Studio when the noise level was high. This defeated the noise and returned to our normal noise floor. Switched the inputs back on and the noise returns.

So your feedback on decoupling the AD1939 CM pin may be particularly relevant. We'll update the cct as you suggest.

IC4 is a TI DRV632 line driver that feeds a 2 channel line output.

RROUT/RLOUT/FROUT/FLOUT are each fed thru a high-gain stage, then rectified/smoothed to feed a signal-sensing standby switching circuit. From memory an input of ~1.3mV will exit Standby and that state remains for 20 mins or so due to C216/R198 timing. FYI there is no host micro on this PCB so standby, protection, power supply management is all taken care of in hardware.

Yes, we'll get some examples of the noise floor spectrum in 'good' and 'bad' modes. We can probably arrange that on Monday as the factory is closed now.

The programs loaded from EEPROM and SigmaStudio are the same. I need to double-check, but I believe that if the circuit boots with a high noise-floor we can load up any profile via SigmaStudio and the noise remains high. If the circuit boots with a low noise floor then the noise floor will remain low regardless of any profile we load via SigmaStudio. This would make sense if the AD1939 is the source of the noise.

We also found today that the ADC input filter values differ significantly from those specified in the AD1939 app note. We've ordered the correct values and will check these too.

As a footnote I should mention that the design was provided by the manufacturer of the amplifier so we don't have any development history with this part of the circuit until now.

Thanks again

Stuart

I've got the noise floor spectrum from the factory now. To keep things simple these were taken from the outputs of the analogue line drivers to avoid any contribution from the Class D power amps. There are two attached. The 'Lower noise' plot shows the noise floor when the O/P noise measured around 0.9mV. The 'Higher Noise' plot was taken when it booted with a higher noise floor of 1.3mV.

We can now see that this problem is not directly attributed to the DSP profile. Just that some profiles we install are making the difference in noise levels easier to see. There always appear to be two discrete noise levels as in these examples and we can see either when the system starts. We have tried your recommendation to decouple the AD1939 CM pin per the application note and this doesn't appear to fix the problem.

Appreciate any other ideas you may have or tests you can suggest we make.

Stuart

Hello Stuart,

Thanks for the information. It looks like you did eliminate the outputs and amplifiers by muting the ADCs.

I am wondering about power. I see two different power nets, the 3.3VV and 3.3VD. I also see that you are not using the on-chip regulator on the AD1939.

So I am wondering what is the timing of these power rails? How closely do they power up?

The codec would like to see the AVDD be first and then the DVDD. They could be at the same time but usually it is an issue if DVDD comes up first. I would have to check with the designers since this datasheet does not go into these details. Then the codec would have to see a master clock to perform its initialization and this will happen after the reset delay and then after the DSP program is loaded and the CLKOUT becomes active. I don't see that as a problem because the codec is in standalone mode and so nothing will be trying to "talk" to it before it is done with its initialization.

So this is a bit of a head scratcher.

So look at the timing of the power up of AVDD and DVDD.

Then also use a good high impedance scope probe and look at the LF pin. This is the loop filter of the PLL. If you see any kind of ramp or sawtooth signal then it means the PLL is not locked. This could be a clue. See if it is different when bad and when good.

Thanks,

Dave T

Thanks for these ideas. For the moment I've strapped AVDD and DDVD together. May not be ideal from an audio point of view, but perhaps the quickest way of eliminating any problems with the relative power up times of the two rails. Since I did that one of the regs is feeding all the power (it's much hotter), but it's handling the demand OK. With this set up the noise is still switching between two levels unfortunately.

One other consideration is that we have the capability to manually reset the DSP and CODEC as the STM811 reset IC has a tact switch connected. If we leave power applied to the cct and blip the switch to reset the DSP and CODEC we still get shifting noise in pretty much the same way as we do with a cold-boot of the amp. That got us thinking that there may be a problem with the reset cct, but it's pretty simple.

I've probed the PLL and there's no sign of any sawtooth or ramp. There's also no discernible difference when the noise changes state.

Then I took a shot at bypassing the DSP so have wired the two DATA out lines from the ADC to two of the DATA in lines for the DAC. One feeds on to a power amp, the other feeds line out. With the DSP bypassed the noise problem is still there. Appreciate the DSP is still generating MCK, BCK and LRCK, but with the data routed round it the noise level is still shifting.

In case it's of interest I've uploaded a couple of scope shots that show the relative timing of the digital audio from the CODEC. The 'audio data from codec' photo shows LRCK, DATA and BCK for a large amplitude signal, synced to LRCK. The 'clock signals' photo shows the relative timing of the LRCK, BCK and the MCK feed to the CODEC. These look OK to me and the relative timing stays the same for low or high noise levels.

What he have confirmed is that the boot noise state after reset can't be changed once the hardware is running. So if it resets with high noise then it stays with high noise. Likewise with low noise. So far we haven't yet found any way to change between states except a further reset.

Thanks again

Stuart

Hello Stuart,

Thanks for the scope plots. It looks to me that the BCLK high to low transition is slightly before the LRCLK high to low. And I do mean slightly. This reminds me of an issue I troubleshot with this codec in an application where the PLL was not locking but was close. The BCLK edge would move around a little and if it was early the DSP (Not a SigmaDSP) was programmed to look for the falling edge of the BCLK AFTER it saw the LRCLK edge fall. This would make it skip two BCLK periods before looking for the data. This made the receiving device miss the MSB and that effect is to lose one bit of resolution. Interestingly enough, I looked at your FFT data yesterday and it looked like the noise floor was exactly one bit higher. So we may be on to something.

Do you have any series resistors or caps to ground on the BCLK line that you do not have on the LRCLK line? Even though the LRCLK is a much lower frequency you should treat them all the same for timing reasons.

Then can I see your PCB layout around the codec? The top layer. I assume you have a power and ground layer and then a bottom layer as a minimum layer count correct?

Dave T

Hi Dave

Thanks for the suggestions. It occurred to me that I had been using an old-ish scope probe for LRCK in those previous scope shots so I've re-done them today showing just LRCK and BCK using identical probes and closing right in on the edges. The photo is attached with a cursor dropped on and they are really well aligned as you can see. I think any misalignment you could see before may have been caused by this.

I then moved on to check MCK vs BCK with identical probes and this proved interesting. The scope photo is attached. I'll always check both low and high noise modes once the scope is hooked up in case I can see any difference, but this time I couldn't get the cct to flip into high noise mode when the scope probe was attached to MCK. Remove the probe and I could get high noise mode as usual. So it seems the loading of the probe on the MCK line is linked to the high noise mode.

Checking the schematic I can now see there's no resistance in this line so MCK out from the DSP is wired directly to MCK in of the CODEC. That won't be good news for the MCK signal, nor for EMC performance! Crazy that they took care of all the other digital lines, but not the MCK feed. We think this may be relevant so I've asked the factory to drop in a resistor at the DSP MCK source if they can to check this. I'll also try the same experiment here when I get some more time later.

Suggest you hold any time on the project for now until we have more news. If this looks promising we'll run some extensive tests before confirming, if not we'll follow up the actions from your last note. Will keep you up to date.

Thanks again

Stuart

Apologies, forgot the scope traces....

Hi Dave

We've made a few changes to the circuit now.

We've added a 100R source resistor in the MCK feed from the DSP to the CODEC (this was missing, but adding it in didn't fix the noise problem).

The AVDD power supply at the CODEC was quite noisy with a 130kHz imprint which we found was sourced from the power supply for the EEPROM that stores the profile for the DSP. AVDD was powering the analogue section of the CODEC (including PLL), but also some of the digital circuitry including the EEPROM and reset IC. The layout made it quite easy for us to leave the digital circuitry running from the existing AVDD, then hook up a new, separate regulator to feed the CODEC analogue supplies including PLL. With some additional decoupling at the EEPROM the 130kHz imprint is much reduced on the digital supplies and no longer visible on AVDD at the CODEC, but this still didn't fix the noise.

You did ask about source resistors and capacitive loading on the BCK and LRCK lines. The arrangement for these looks a bit odd. As far as I can tell they have summed the two LRCK lines from the DSP to the ADC into a node (ALRCK) via 47R resistors. Similarly the three LRCK lines from the DSP to the DAC are summed into a node (DLRCLK) via 47R resistors. ALRCK and DLRCK are then sent to the ADC and DAC, but they have also strapped the ALRCK and DLRCK nodes together via a 47R resistor. I can't see why that was necessary. BCK is handled in exactly the same way. I may try removing the 47R between ALRCK and DLRCK unless there is a good reason to keep this in place (and same for BCK).

The DATA lines are much simpler with just 100R in series with each.

There is no capacitive loading on any of the lines.

You asked about the PCB layout. As we didn't design the PCB we don't have the artwork, but I'll request it. AFAIK the PCB is only double sided. Most of the tracking and components are top side, the underside is mostly ground plane with a few decoupling capacitors direct to the plane under areas such as the DSP.

We're still finding that when we probe MCK the noise floor can shift and this is the only way we can change the noise floor 'live' without re-setting the cct. If the noise floor is high it can reduce when probed. If the noise floor is low it will stay low when we probe MCK. Sometimes the noise floor can flip from high to low (and stay low) when we probe MCK. It's almost as though the timing of MCK is marginal somehow and the probe capacitance is skewing the edges just enough to fix it.

Hello Sam,

The ALRCLK and DLRCLK need to both be driven since the ADC and DAC sides of the codec both need their own clocks. There is no internal connections between the "sides" of the codec. So often the ADC is the master and it will drive the DAC side of the codec and the DSP so those connections seem fine. The resistance might be on the high side as are the 100 ohm resistors you mentioned. Often I see them in the 11-47 ohm range with 33 ohms being common. To properly calculate the resistors required you have to model the circuit with Hyperlynx or similar software. You need the IBIS models for the parts involved and the very detailed trace length and impedance of the traces. Then you can adjust the resistors to be the exact value required.

Having said that, you will never be able to do this because with no ground or power planes in the PCB the trace impedance will be undefined. The root of the issue will be PCB layout issues and step one will be to add two layers to the PCB, a ground and power layer. Then properly terminate the transmission lines and proper placement and routing of the bypass caps on the power rails. You are getting a lot of ground bounce so connecting the probes will change things and you will see it work or not work. The PLL will also be affected by this noise on the ground and power. So you may be slipping the clocks where you miss an edge, or add and edge, and then the timing is off and you are missing bits in the data.

This is hard to describe but they will have to change the PCB layout and I would be glad to have a look at it and offer my opinion.

I wish I had better news but you are trying to paddle your boat upstream.

Dave T

Hi Dave

Thanks again for your time on this. It's quite difficult for us as we don't own the design of the circuit or the PCB - this was prepared by the supplier in China.

How confident are you that a PCB re-spin that included power and gnd planes would fix this problem? I would expect the supplier already has significant stock of the existing PCB that would need to be written off so I wouldn't want to recommend this unless I could be fairly certain this would fix the problem.

Stuart

Hello Sam,

I am very confident. I have seen problems where it was simply the way the bypass caps were placed and how traces were run caused a similar problem. Changing the PCB layout fixed the problem. This particular case they had a multi-layer PCB and ground planes so in your case it is even worse.

Have them consult with me on the PCB layout.

Thanks,

Dave T

Hi

We've got some good news on this. The supplier has agreed to re-spin the PCB on 4 layers and is also re-locating the master clock to the CODEC (it's currently at the DSP). I'm hoping they'll agree to release the artwork for checking before prototyping the PCB.

Stuart

Hi:

from the looks of the first post in this thread (and without reading through all the thread), I looks like there might be a dynamics processor with slow time constants in the signal flow that make the floor show up at cold (or when the signal flow is reset). This might be alleviated by carefully setting the proper default parameters of the dynamics processors in the signal flow OR by speeding up the time constants (perhaps temporarily) to make the dynamic nature of the dynamics processor rapidly converge at init.

Just a thought.

Regards