ADAU1761 PLL lock
Hi,
My customer is using ADAU1761 for BT handsfree application. They encountered PLL lock issue. Some unit can detect PLL lock. Some can not. What could be the possible reason lead to such problem? I attached its PLL initialization code and power sequence code for reference here. Kindly please advise.
Thanks
Audio Signal Processors
SigmaDSP Audio Processors
adau1761
Hello Keddy,
It looks to me that they are waiting 2.96ms for the PLL to lock. This is the typical time and it could be longer. In some places it looks like the code is waiting for the lock to happen. It is a little tough for me to follow the code. So they need to check for the PLL to lock and not just wait a certain amount of time.
Also, it looked like they were checking the PLL then after it was ready it was changing the 1761 over to SPI mode. Which means to me they were not configuring or reading the PLL at all because it needs to be in SPI mode first before that can happen. So I am not sure I am reading this code correctly.
What I cannot tell from the code is how long are they waiting for the part to power up and be ready? This is the time from when power is applied to when they try to first communicate with the part? This will depend on factors in the design of their board. In the datasheet it states around 14 ms if there is a 10uf cap on the AVDD line. So they need to wait for power to be reliably up and the part's POR (Power Up Reset) has completed. Then change over to SPI, configure the PLL and start it up. Then wait for it to lock by checking for it in a loop. Have an exit if the lock never happens but they need to wait a long time for that exit on failure. I would make it be 30ms or so. It should lock well before that and the program will proceed but give it plenty of time in case there are issues. Temperature and interferences can cause problems.
You may have to look at this on a scope to see the actual timing.
Dave T
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