ADAU1761 TDM8 Master mode problems
We have set up an ADAU1761 as followsi
TDM8 mode.
bus master.
LRCLK is set to pulse
BCLK cycles to 256
BCLK as falling edge
Delay of 1bit
No data comes out when LRCLK is set to rising edge.
Data comes out when LRCLK is set to falling edge.
if LRCLK is set at 50% it will work on rising or falling edge
This has been checked on an eval board through Sigma Studio and on our prototypes by setting register 0x4015.
This seems very strange as TDM requires rising edge polarity on LRCLK as pulse.
If we set delay to 0 bits and LRCLK falling edge the data looks to be changing on the rising edge of LRCLK
Audio Signal Processors
SigmaDSP Audio Processors
adau1761
Correction
When set to master, pulse mode, TDM8, delay of 1 bit, with LRCLK set to falling edge the data is clocked out on the rising edge of the pulse.
When delay is set to 0 bits the data is clocked out one bit before the pulse.
TDM requires the data to be clocked out one bit after the rising edge.
Is there some setting I have missed?
The above was observed on a dev board which doesnt have the 47p capacitor on LRCLK, when added in the data is coming out with the correct 1 bit delay.
However there is still the problem that data does not come out when register 14 bit 3 is set to select rising edge.
Is this the way pulse mode works on the ADAU1761? ie as there is only one valid lrclk polarity in pulse mode there is no need for a polarity control, if so why does setting the polarity bit kill the output?
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