How to set the clkout sync with BCLK on ADAU1451?
Hello Guys,
I have set the CLKOUT 12.288Mhz and Fs is 48kHz. However, my salve device can't accept MCLK is not sync with
BCLK situation. How to set MCLK sync with BCLK? By the way, the offset of MCLK is differ when every time is initaialized.
Please check the wavform.
Audio Signal Processors
adau1451
SigmaDSP Audio Processors
Hello J.chen,
The MCLK edge is not required to be synchronized with the I2S signals, only that the required number of edges happen during one LRCLK period. (one frame). Remember that we use an internal PLL for the clock reference and that it locked to the MCLK frequency but not the exact edge.
So now since it appears that another device in your system requires an MCLK that is precisely locked to the edges of the serial clocks, I propose you use the BCLK pin of either an unused port (it can be an input or output), or a port that is set to TDM8. You set that port to be a master at 48kHz and it will produce 12.288MHZ that is aligned with the edge of the LRCLK. You can even adjust the polarity. This trick has been used in designs and it also has some other advantages. You have control over it and can gate it if desired. I think this will solve your problem as long as you have an available port.
Dave T
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