adau170x Digital ouput block issues

Hello Sebastiaan,

First it would be good to make sure I know what your are intending to do. It sounds like you are using the I2S mode of serial transmission, not the TDM mode. So make sure you do not have the "TDM Enable" box checked.

So in I2S you have two channels on SDATA0 and two on SDATA1. You have the MP pins set correctly and in SigmaStudio Dig0-Dig3 will show up on these first two serial ports.

It sounds like you are running the 1701 as a slave to the DSP. This is fine as long as you are set to slave. Since you are getting data you are set properly.

I see some confusion in your text. If you want all eight channels out of the DSP to be on one serial stream then you need to be in TDM mode. Then you will only be using SDATA0/TDM_OUT pin. All eight channels will be there.

You then have to set the DACs to the same format. You may also run into the problem where some TDM implementations are slightly different. IF you look at figures 35 and 36 in the datasheet you will see the eight TDM slots shown. Some parts will output the odd channels on slots 1-4 and odd channels on slots 5-8. This might be what you are experiencing.

The other explanation is that you have the 1701 in standard stereo I2S and the DACs in TDM mode with one set to pick up the first four and the other set to pick up the last four. Then switching the clock polarity would switch to the other part. I have not read the PCM datasheets but look closely at the settings for the parts. Then also look at the clock rates.

I suggest you take a scope and make some scope plots and look at the data. Look at the LRCLK, the BCLK and the data at the same time on the scope. Trigger to the LRCLK and you will see how the data is organized.

So give me some more info like the clock frequencies and desired formats? You also could include your SigmaStudio project or screenshots of the settings.

Dave T

Hello Dave,

Thanks for the reply.

To clarify my setup, I'm developing a 1 in/4 out xover, with a PCM4201 ADC and PCM4104 DAC. I'm using only 1 channel of a I2C stream for the ADC, and using 2x2 I2C streams for the 4 outputs. The dac is connected with MP 6 and 7 for the datastreams from the DSP. So I'm not using TDM and this is swithed of in the registry. The ADC stream is left-justified.

I also fidled around with some settings/options the last few days, and I think the issue is in a not corresponding sample rate capability between the ADC and the DAC.

The DSP is set as master, and is running on a 12,288Mhz clock with 256xFs on 48kHz. According to the DAC datasheet this is no issue for the DAC and is set to single rate in hardware mode. I can output all 4 channels on the DAC on Dig0 till Dig3, with the registry set to:

LRCLK Polarity = All output function, in both settings.

BLCK Polarity = Output only functions by selecting "falling edge"

Frame Sync type= LRCLK

MSB position = Delay by 0

Frame sync frequency = Int.clock/1024

BCLK frequency = Int.Clock/16

The weird thing however is that they say the following in the datasheet:

"For Standalone mode, the LRCK polarity is always normal, while the serial audio data

is always sampled on the rising edge of the BCK clock."

But if I select rising edge, there is no output at all

For the ADC (I check realtime if there is any signal comming into the DSP by a level meter inside sigmadsp) I only get a signal if I set the BLCK frequency to Int.clock/8 when set to normal rate/High performance mode. But the I don't have the 4 outputs available on the DAC, without switching between LRCLK polarity and only on DIG0 and DIG2.

This is from the PCM4201 datasheet:

"Slave mode operation requires that the FSYNC and BCK clocks be generated from an external audio processor or master timing generator, as shown in Figure 5. Both clocks are inputs in Slave mode. The FSYNC clock rate is the equal to the desired output sampling frequency, fS. The FSYNC high pulse width must be equal to at least one BCK

clock period. The BCK clock rate should be 128fS for Normal Speed, High Performance sampling mode. A BCK rate equal to 64fS results in no output for this sampling mode. For Normal Speed, Low Power sampling mode, the BCK rate may be 64fS or 128fS. See Note (2) in Figure 3 regarding the FSYNC edge used for start of frame when BCK = 128fS for this sampling mode. For Double Speed sampling mode, the BCK rate should be 64fS"

Now I have set the ADC to Normal rate/low power mode and then I can set the BLCK frequency to Int.clock/16 and I have all 4 outputs to the DAC... You would say it is solved then... But not quite.. I really need the ADC set to Normal Rate/High performance mode for the higher dynamic range. Then I only get a signal from the ADC when the BLCK frequency is set to Int.Clock/8, but then the DAC 4 outputs won't work, on DIG0~3 only on DIG0 and DIG2 and by switching between the LRCLK polarity...

Also some time when loading the program into the DSP with the ADC set in Normal Rate/Low power, I get strange peaks in my signal outputs of the DAC, which are clearly seen while inputting a sinewave. If I switch between the LRCLK polarity in the registry, then these peaks dissapear and the sine wave looks normal...

I'm confused how to solve this issue... I hope you have the solution, or where to look next..

Sebastiaan