ADAU1701 DAC clock driven from PLL or MCLK ?

Hello Koen,

You issue is actually very difficult to solve. Your basic question about the DAC clocks is yes, it is derived from the system clock. So if the system clock has a lot of jitter then so will the DAC clocks.

To help you with your problem is a bit more difficult. Most SPDIF receivers will have a PLL so is that output really bad? Have you measured the jitter to know the amount and the distribution of the jitter? I am not sure of the loop filter/PLL design of this part enough to know where it best rejects jitter and where it does not. This part was designed a while back so I will have to ask around and see if that info is available.

Meanwhile, I will suggest some things for you to try. Does the SPDIF receiver have the ability to change the MCLK output frequency? The 1701 can operate using 64x, 256x,382x, and 512x fs modes for MCLK. This may move the jitter out to a place where the PLL can better reject it. However, the LRCLK and BCLK out of the SPDIF receiver will still be jittering and I am guessing the 1701 is running as a slave? This brings you back to trying to clean it up at the source, the SPDIF receiver.

Some of our newer SigmaDSPs have a sample rate converter which helps to combat this issue.

Now, I want to move over to other hardware issues. I have seen where poor signal integrity and poor power and ground filtering in the design coupled with PCB layout issues can cause jitter related issues and DAC performance issues. So you may be fighting wider issues than just the SPDIF receiver. So are there other audio sources in your design that are going to the DACs and performing well?

Let me know what you have tried so far?

Thanks,

Dave T

I'm using the AK4113 receiver. the phase noise and spectrum of the the clock at 24.576Mhz are attached. the spectrum is a typical locked signal.

when I short the receiver input, the PLL drops out of lock and the xtal clock is forwarded to the DSP instead. then the DAC noisefloor is clean. the design uses a DCDC suppply , but this is not visible in the dac noise floor.

I've done more designs with the 1701 and switching supplies and never saw any problems.

I still need to check if the receiver is compromised by the onboard dcdc running at 275Khz, but my gutfeeling says that this is the usual clock quality coming from the AK4113 pll. there is no external access to the loopfilter of the AK4113.

what remains is the 1701 loopfilter, if we could give that a Hz range bandwidth to clean up the reveiver clock.

but I'm getting close to design in a sample rate converter to be able to run the 1701 as master with a clean xtal clock

Hello Koen,

I talked to the engineer who was involved with the PLL design in this product. He was not comfortable with trying to "tighten up" the loop filter of the PLL. He did say that yes, it can be tightened up to improve the performance and reject the jitter but there are negatives that go along with it. The first being an increased lock time for the PLL. Then he said you could tighten it up for the one part using selected components but then if you look across process skews, temperature variations, variations in the loop filter components etc., it may become a production issue for you down the road. So I would take his hesitancy as a sign that this is the wrong direction to travel.

It is interesting that one of the first comments he made was to ask if you were using an AK part? His suggestion was to change to a different SPDIF receiver. We use a Cirrus part in our evaluation boards and they have reasonable performance.

You may be aware that we have a couple of DSPs that have an SPDIF interface built in. There are some limitations but I assume your application is power sensitive or cost/space sensitive? If you want to look into alternatives I can help you with that.

Thanks,

Dave T

dave,

thank you for these useful suggestions. I would need a really narrow loopfilter to clean up the jitters. PLL clocks have a hard time to compete with crystal clocks, unless there is a narrow lock range and crystal based VCO's.

The AKM chips are apparently compromize between large lock range, chip area and PLL noise.

I read a comparison between wordclock syncd soundcards and the same autonomous crystal clocked soundcards. almost all did perform worse with a wordclocked pll. IMHO a masterclock distribution would do much better.

(AKM or other) sample rate converters are cheap and a better final solution at is allows to run the DAC on local cyrstal clock. long twisted pair cable runs of the SPDIF have no effect on the DAC performance this way.

This is a very useful discussion as the SPDIF derived clock quality has been a missed item in the pure sound world. we seem to forget that the precision of 1bit dacs is coming from the precision in time.

koen

Hello Koen,

All very good observations. I agree that the quality of the SPDIF derived clocks is often overlooked.

So it sounds like your design constraints can absorb the added costs/space for an ASRC. So that is probably the best solution for you.

One thing I forgot to mention is that the other DSPs with SPDIF receivers also have built in ASRCs. They just do not have built in ADCs or DACs.

Thanks,

Dave T

Dave,

a note on the cost side. what puzzles me is that the ADAU1701 can be bought in china for 4 euros per piece, shipping included (in lots of 5), that is half of what any distributor charges for volume qtys( let alone shipping costs).

the ASRC (AK4127VF) is 1.5 euro in lots of 20 ..

The versatitly of the 1701 is limit-less. for example I built a cosphi corrector for a current transformer measuring the current trying to regulate the contribution of a solar converter to maintain zero-feed-in. the ADAU measured both the current transformer and the voltage information, and calculated a real power equivalent amplitude synthesised 50hz current. just a fun project using sigma tools. a huge improvement over the first 56K motorola project I did in assembly back in 1992. (a medical telemetry SDR )

thanks again

Koen

Hi. This really does sound like signal integrity issues on your PCB layout.

I have done quite a few PCBs with SPDIF and Cirrus or AK DACs with noise floor of -115 to -120db without issues.

However I have not tried AK spdif receiver, only Cirrus or AD receiver.

Be careful that the Serial signals from the spdif receiver are correct phase and polarity and format to match the DSP. you might be in a marginal timing space.

regards

Brett