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Q&A from Analog Devices EngineerZone: SigmaDSP/SigmaStudio and DSP discussions (23 topics).
23 topics · 113 messages
Filtered by: #pll ✕
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ADAU1462-150 PLL and other settings
Hi, I was starting implementation for the ADAU1462-150 and came accross some points that are unclear for me. 1) The datasheet shows in Table 20 on page 29 the predivider and feedback divider settings.
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Problems setting PLL up on ADAU1452
I am unable to get my custom ADAU1452 board PLL locking. The MCLKIN/OSCIN is driven by a crystal oscillator IC at 3.3V and it looks good on oscilloscope. Checking the PLL lock register never shows loc
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SigmaStudio+ does not apply the “PLL Input Clock Divider” setting to the hex file, so it is not written to the EEPROM
Hello, I have again found a bug in SigmaStudio+2.3.0: SigmaStudio+ does not apply the “PLL Input Clock Divider” setting to the hex file, so it is not written to the EEPROM! Divide by 4” is always writ
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External Master Clock vs I2S
Using ADAU1772, we create a Master Clock with our fpga. It is a little off, 12.262 MHz. I did not change anything in the PLL SigmaStudio tab, wrote the EEPROM with the fpga, and we got the intended si
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ADAU1787 PLL Input Prescaler
When I change the input divider to the PLL (CLK_CTRL2 bits 2:0) between the values of 0 and 1 it doesn't seem to change the clock rate?For verifying clock rates I am monitoring the MCLKO pin. If I am
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ADAU1701 losing PLL Lock
We have had multiple product failures from the field which are due to the ADAU1701 failing to start or maintain PLL lock. This results in static noise being outputting on the DAC. We have faced many i
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ADAU1787 can I have the PLL in power-down mode if PLL_BYPASS=1?
I plan to bring in my own 24.576MHz MCLK to the ADAU1787and I see in the PLL_MB_PGA_PWR register a PLL_EN bit for PLL power. If I have the PLL_BYPASS=1, do I still have to enable PLL power? Thanks, Da
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ADAU1452 PLL lock not working on custom PCB
Hello, everyone! We are developing a board with ADAU1452, which includes AD1938 and TPA3255. We have a problem: the ADAU1452 does not work on our board, but it works on another debug board nearby. Con
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ADAU1467 does not boot up properly
I'm working on a board with an ADAU1467 acting as an audio processor, and programmed with SigmaStudio 4.5. I'm currently stuck with a weird bug where I have several boards that will not program. As in
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ADAU1467 does not boot up properly
I'm working on a board with an ADAU1467 acting as an audio processor, and programmed with SigmaStudio 4.5. I'm currently stuck with a weird bug where I have several boards that will not program. As in
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AD1939 Failing to Verify PLL Lock ADSP-21489
Hi, I am working on an audio design using the AD1939 codec alongside Sharc ADSP-21489. The design is largely based on the audio features present in the ADSP-21489 ez-kit, as are the schematic and layo
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PLL Filter reference to VDD or GND?
Hi. I am wondering why the PLL filters on e.g. the ADAU1451 and ADAU1701 are supposed to refer to VDD. In both datasheets, the PLL Loop Filters are specified to refer to VDD (Digital or PLL VDD), but
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ADAU1701 PLL modes for 45.1584 & 49.1520 MHz MCLKs?
Hi guys, hope you could help me figuring out, if a allo kali reclocker with its 45.1584 & 49.1520 MHz MCLKs is compatible to the ADAU1701 and if so, which PLL_modes to use (s. Setting the PLL mode for
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PLL Enable/Disable not working when selfbooted
adau1452 i2c selfboot Hello Community, we are having problems when trying to disable and re-enable PLL after ADAU1452 has self booted through I2C eeprom. Here is a brief description of my project: I b
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ADAU1701 DAC clock driven from PLL or MCLK ?
I have a ADAU1701 design with the MCLK driven from a dirty clock from a spdif receiver. this affects the noise floor of the DAC severely. I hoped that I could clean up the DAC clock by decreasing the
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1701 PLL filter ... How to verify it's working?
Hi everybody, I've a problem with a set of boards using the 1701. Due to design constraints we use a 24.576Mhz clock (an XO module), connected to the master clock input.Of course the PLL mode pins are
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ADAU1761 - How would you do a Phase Locked Loop?
Hi everyone, I did my own version of a Phase Locked Loop, like normally used for frequency modulation. Everything works fine in SigmaStudio, but when I transport it to a microcontroller I have some bu
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A -1701 FM MPX Demodulator
This is a just-for-fun project, for which no claims are made that it's optimal. I just drew it up in half an hour a few months ago, and then tweaked the thing until it worked. The incoming composite s
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How to control ADF4351 evaluation board by Matlab
We are trying to build communication between the ADF4351 evaluation board and Matlab. One of our options is to use I2C/SPI adapter, but we want to control this evaluation board by only using USB cable
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MCLK to ADAU1761 cannot be locked in Sigmastudio
Hi All I am developing a project for ADAU1761 . A active OSC =24.576MHz clock connect to MCLK pin. Now LINK and COMPILER , verify PLL status always keeps unlocking. checked the 24.576MHz clock by scop
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about the PLL fractional mode in ADAU1361
Hi,guys, I'm now using ADAU1361 eval board , and SigmaStudio 3.6. And I found that if PLL fractional mode is used, and that fractional part value is too small(i.e. 0.0001), the PLL could not lock. See
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ADAU1761 and ADAU1361 MCLK Range and PLL Range
I am looking for the lowest MCLK frequency that the ADAU1761 or ADAU1361 can operate with. I see in the spec the following: 488nsec period = 2.05MHz... Meanwhile, the front page of the datasheet shows
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ADAV400 PLL filter components
Hello. I have designed a board with couple of ADAV400 and AD1702 DSPs, and AD1974 ADCs. DSPs are clocked with 64 * fs (3.072 MHz) and ADC generate iternal clock from LRCLK. PLL filters of all chips ar