ADAU1761 and ADAU1361 MCLK Range and PLL Range

You will notice that on the front page of the datasheet, the PLL range is defined as being between 8 MHz and 27 MHz. However, the MCLK range is defined as going down to 2.05 MHz.

The reason for the two independent specifications is that the chip can operate in two clocking modes: PLL mode, or bypass (direct MCLK) mode. In bypass mode, you input a master clock directly to the ADAU1761's DSP core (or the ADAU1361's clock generators).

In the case of Table 7, the master clock range being defined is for direct MCLK mode (bypassing the PLL). Each row in the table shows that this range applies for an MCLK at is a multiple N of the sample rate, with N = 256, 512, 768, or 1024. For each row, the minimum MCLK frequency is for a sample rate of 8 kHz. The maximum frequency is limited by the physical and electrical characteristics of the IC.

In the case of the example, using the absolute lowest MCLK frequency of 2.05 MHz, this spec applies to 256 x Fs mode. This means that there are 256 master clock cycles per audio frame, so the sampling rate is 2.05 MHz divided by 256 equals 8 kHz.

In the ADAU1361, this is a valid way of operating the chip. However, for the ADAU1761, which includes a SigmaDSP processing core, various problems arise.

The main disadvantage to running the ADAU1761 in this way is that the DSP can only execute 256 instructions per sample, instead of the usual 1024. This effectively reduces the DSP processing power to 25% of its potential.

If you want to use the lowest MCLK possible, but still maintain the full functionality of the chip, then I would suggest using the PLL and inputting an MCLK frequency down close to the 8 MHz limit.

This question has been closed by the EZ team and is assumed answered.