ADAU1451 serial ports clocking in a slave mode
Thread Summary
The user inquired about configuring clock domains for slave mode I2S and TDM16 serial ports on the ADAU1451. The final answer directed the user to the data sheet, specifying the BCLK and LRCLK pairs for each clock domain. The accompanying answer clarified that in master mode, the integrated clock generators can be used to configure the clocks, with settings found in the SigmaStudio under ADAU145x Register Controls -> CLOCK_CONTROL.AI Generated Content
Hello,
in a current design I use ADAU1451.
Some of the serial ports are supposed to work in a slave mode (some I2S, some TDM16).
According to the Sigma Studio in a slave mode I need to assign BCLK and LRCLK for the slave IN and OUT ports to one of the 4 clock domains 0 to 3.
I couldn't find where these clock domains are configured and how.
I see clock generators setup, but can't figure out if these are related to the above serial ports clock domains and how.
Will appreciate any clarification of this issue.
Gennady
Audio Signal Processors
adau1451
SigmaDSP Audio Processors
Hi,
just take a look on page 60.
http://www.analog.com/media/en/technical-documentation/data-sheets/ADAU1452_1451_1450.pdf
Corresponding Clock Pins in Slave Mode:
BCLK_IN0/LRCLK_IN0 = Slave from CLK clock domain 0
BCLK_IN1/LRCLK_IN1 = Slave from CLK clock domain 1
BCLK_IN2/LRCLK_IN2 = Slave from CLK clock domain 2
BCLK_IN3/LRCLK_IN3 = Slave from CLK clock domain 3
BCLK_OUT0/LRCLK_OUT0 = Slave from CLK clock domain 0
BCLK_OUT1/LRCLK_OUT1 = Slave from CLK clock domain 1
...
In case LRCLK/BCLK is master, you can generate the clock with the integrated clock generators.
Configuration on page 30. SigmaStudio: ADAU145x Register Controls -> CLOCK_CONTROL.
For an example, if you use a 294.912MHz system clock and CLK GEN 3 is set to N=49, M=320 and you choose "BCLK/LRCLK is master" for a serial output port, you can select "Clock Generator 3" and "Sample Rate FS" = 44.1kHz. (2*FS=>88.2kHz, 4*FS=>176.4kHz, ...)
best regards,
fio
Thank you, Heidi
yes, I looked at that description.
It tells me which BCLK, LRCLK pairs are used for which domain in a slave mode.
But it doesn't mention anything about configuring clocks for these domains.
It's pretty clear for the master mode - no domains are assigned.
Is it possible that clocks for the domains in a slave mode are configured by assigning TDM mode type ?
This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.
Thank you,
EZ Admin
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