ADAU1761 TDM8 audio slots
Thread Summary
The user is experiencing an issue with the ADAU1762 in TDM 8 mode where audio slots are assigned as Dig 0, 2, 4, 6 for the left phase and Dig 1, 3, 5, 7 for the right phase. The final answer confirms this is the expected behavior due to the part's clock polarity and stereo pair splitting. The user will need to unscramble the slots in the DSP to achieve the desired order. No specific workaround is available, but newer Analog Devices parts do not exhibit this behavior.AI Generated Content
I have an ADAU1762 set for TDM 8 mode.
According to the data sheet audio is transmitted out in order slot 0,1 2 etc to 7.
What I have is coming out in the following order:-
DIg 0, Dig 2, Dig 4,Dig 6, Dig 1, Dig 3, Dig 5 and Dig 7.
Ie it seems to be assigning odd Digs to the Left phase and even Digs to the Right phase.
I get the same results using LRCLK or Pulse.
Is this correct and something I just have to be aware of in my design or is there some setting I have missed that puts them in numeric order.
I haven't tried the input signal yet, should I expect them to obey the same rule?
Audio Signal Processors
SigmaDSP Audio Processors
adau1761
Hello Colin,
Yes, this part fills in the left channel data when the LRCLK is low and right channel when it is high. So the first stereo pair is in slots 1 and 5. The second stereo pair into 2 and 6 etc. Then there is the issue that the normal clock polarity for TDM is having the clock go high at the start of the frame, and also just be a pulse. So that is why you are seeing the right channel first then the left channel.
You can always change the clock polarity and then you will at least get the left first then the right. But there is no way to change the splitting of the stereo pairs.
So you will have to unscramble it in the DSP so it comes in and out like you are thinking. Our newer parts do not use this scheme for TDM data.
Sorry for the confusion.
Dave T.
Thank you Dave.
As long as I know about it then I can deal with it.
Please log in to reply.