Internal impedance for ADAU1761and ADAU1401A BCLK port

Hi,

I have moved this discussion from the Processors and DSP community to the SigmaDSP Processors and SigmaStudio Development Tool community. Please continue the discussion here.

Regards,

Craig.

Hi,

The ideal impedance for the entire pathway of a clock or data line would be 50 ohms, and our clock/data ports conform to this value. Optimizing your overall circuit for signal integrity and EMI performance can be performed using an IBIS model for the particular devices, in conjunction with simulation software which will allow you to take the physical pcb into account. If you do not have these resources, I have a very simple recommendation:

The frequencies of BCLK, LRCLK and SDATA signals are in low enough that a simple series resistor, placed near the source, provides ample termination to the signal. I would recommend that you start with 20 ohms, build your circuit, and then use an active scope probe to look at the actual signal on the board. If you have any ringing or overshoot, increase the value of the resistor until it goes away. If the signal does not have a sharply defined leading edge and is too rounded, decrease the value of the resistor.

In every case, keeping your traces short, using 4-layer boards with solid internal planes for power and ground, and using appropriate power supply decoupling on all of your Vdd pins will help to yield a successful design.

Regards,

Coleman