ADAU1761 I2S slave mode with non-synchronous MCLK

Hello John,

According to page 26 of the data sheet under Core Clock,

Clocks for the converters, the serial ports, and the DSP are

derived from the core clock. The core clock can be derived

directly from MCLK or it can be generated by the PLL.

Thus, whether the PLL is used or bypassed, the two chips need to be synchronized via MCLK. Thus the statement on page 42 doesn't tell the whole story. You can get MCLK from the crystal oscillator output (pin 31) of the -1701, however you'll need to buffer this signal since it's not intended to drive other inputs directly.

Best regards,

Bob

Thanks Bob - helpful as always.

So you think that the noise problems that I am experiencing are due to the two clocks not being synchronised? I am beginning to think you are correct as if the sampling rates are slightly different the system must miss samples at some point to re-synchronise. If the PLL frequency is not derived from the from the input I2S BCLK then it cannot correctly receive a different sampling rate without the usual process of re-sampling and filtering.

So can someone explain to me why there is the following text box in the SigmaStudio environment? In the Hardware Configuration on the last tab "DSP registers" there is a DSP Sampling Rate Setting (second box down in the middle column) which can be set to "Serial Input Data Rate". What does this do?

On further investigation I think I can answer my own question. Register R64 controls the sampling rate of the serial port which can be different to the rest of the system but is still derived from the MCLK oscillator. So you are correct Bob - a common MCLK or clicks and bangs as the clocks beat against each other.

Regards

John

John,

Actually it does seem that using the "input sampling rate" choice, the PLL would attempt to sync to the incoming I2S -- then the page 42 blurb would be quite correct. I'm afraid I got over my head on this particular chip.

I'm not familiar with the -1761 eval board and presently have not enough time to look it up. Likely the -1761 gets its MCLK either from an on-board codec or its own oscillator. Having two nearly equal clocks in the system, even with the above PLL choice, is a potential source of trouble. Syncing the MCLKs is still a good idea overall, although this may be difficult using eval boards if a codec is involved.

Bob

Bob

The 1761 eval board just uses the ADAU1761 - no EEPROM or CODECs are involved. I still think you original line of argument is correct. The PLL is either an integer or fractional value of the MCLK input. I cannot see anywhere a bit in a register that says to use the BCLK as the reference for the PLL.

I wish the datasheet was clearer - I hate wasting time trying to decided if the chip can do this when AD could have clearly specified whether it can or not.

John

Hi John,

I know I'm a bit late to the conversation, but maybe I can help.

The PLL takes its input solely from the MCLK (master clock) input pin. There unfortunately isn't a way to set it up to take its input from another clock pin such as LRCLK or BCLK. A few of the ADI codecs have this ability (AD1938, AD1939, et cetera), but the ADAU1761 does not.

The datasheet sentence "If the PLL of the ADAU1761 is not used, the serial data clocks must be synchronous with the ADAU1761 master clock input" is referring to the use case where you are supplying a high-frequency master clock signal directly to the MCLK pin and bypassing the PLL altogether. In that case, you need to make sure that the BCLK and LRCLK signals are synchronized integer subdivisions of the master clock signal. However, the master clock signal must still be present. Does that make sense?

I'm making a guess here, but it seems that maybe the serial port can handle slightly asynchronous clocks if the PLL is used - you could then set the DSP Sampling Rate Setting register to "Serial input data rate" or "Serial output data rate". The PLL generates very high frequency internal clocks that allow the serial port to effectively re-clock the data coming in.

I hope that all makes sense. Let me know if anything is unclear.

Hi Yagami

I think you have cleared where the ambiguous "If the PLL of the ADAU1761 is not used, the serial data clocks must be synchronous with the ADAU1761 master clock input" sentence was derived from. I cannot see how even a slightly different sampling rate could operate as the two systems would be operating asynchronously. Eventually the receiver would have too little or too much data and the sample would be skipped. I have decided to pass the data as analogue signals, with all of the associated problems that that brings!

Best Regards

John

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