ΣSigmaStudio Ask AI Русский Log in

ADAU1761 PLL 'LOCK' related inquiry

SigmaDSP & SigmaStudio ADIApproved May 6, 2014 00:00 2 replies Original on forum ↗
ICs: ADAU1761
#audio+signal+processors#sigmadsp+audio+processors#adau1761
Thread Summary

Thread Summary

The user asked about PLL configuration and verification on the ADAU1761, specifically the minimum delay for PLL lock and the purpose of PLLCrlRegister reads. The final answer confirmed that the PLL lock time is not characterized, and the 10ms delay is generally sufficient for integer mode. The read request for PLLCrlRegister is a SigmaStudio artifact, and the final read is likely a double-check to ensure the PLL is locked. The accompanying answer noted that the PLL 'Lock' was detected properly, and allowing time for configuration resolved the issue.
AI Generated Content
Subscribe
ADIApproved Question
May 6, 2014 00:00

Hi,

We have some questions regarding PLL configuration/verification, specifically on detecting PLL 'LOCK'.

1) What is the minimum delay time required for the PLL to settle assuming good
quality MCLK input? Is this characterized?

Regarding the SigmaStudio capture window contents below:

2) The data sheet indicates no register access should occur during PLL
configuration until 'LOCK' is verified. We then assume the 10ms "DELAY" must be
sufficient to insure PLL Lock. Is this true?

3) Near the end of the sequence a PLLCrlRegister read request appears to return
no data. Why is no data returned? Why is this read request issued at this point
in the sequence?

4) The final operation again reads the PLLCrlRegister. This time valid data is
returned indicated 'LOCK'. What is the purpose of this final PLLCrlRegister
read?

Thanks for your help.

-Phil

Phil Burkert

Staff FAE

Analog Devices

------------------------------------- Capture Window Contents -------------------

Block Write
Time: 9:51:36 - 511ms
IC: IC 1
Param Name: IC 1.Sample Rate Setting
Param Address: 0x40EB
Bytes: 1
Param Data:
0x7F

Block Write
Time: 9:51:36 - 521ms
IC: IC 1
Param Name: IC 1.DSP Run Register
Param Address: 0x40F6
Bytes: 1
Param Data:
0x00

Block Write
Time: 9:51:36 - 531ms
IC: IC 1
Param Name: IC 1.Clock Control Register
Param Address: 0x4000
Bytes: 1
Param Data:
0x0F

Block Write
Time: 9:51:36 - 531ms
IC: IC 1
Param Name: IC 1.PLL Control Register
Param Address: 0x4002
Bytes: 6
Param Data:
0x00, 0xFD, 0x00, 0x0C,
0x20, 0x03

DELAY
Time: 9:51:36 - 531ms
IC: IC 1
Param Name: IC 1.Delay
Bytes: 2
Param Data:
0x00, 0x64

Block Write
Time: 9:51:36 - 541ms
IC: IC 1
Param Name: IC 1.Serial Port Control Registers
Param Address: 0x4015
Bytes: 2
Param Data:
0x00, 0x00

Block Write
Time: 9:51:36 - 541ms
IC: IC 1
Param Name: IC 1.ALC Control Registers
Param Address: 0x4011
Bytes: 4
Param Data:
0x00, 0x00, 0x00, 0x00

Block Write
Time: 9:51:36 - 541ms
IC: IC 1
Param Name: IC 1.Microphone Control Register
Param Address: 0x4008
Bytes: 1
Param Data:
0x00

Block Write
Time: 9:51:36 - 541ms
IC: IC 1
Param Name: IC 1.Record Input Signal Path Registers
Param Address: 0x4009
Bytes: 8
Param Data:
0x00, 0x01, 0x05, 0x01,
0x05, 0x00, 0x00, 0x00

Block Write
Time: 9:51:36 - 541ms
IC: IC 1
Param Name: IC 1.ADC Control Registers
Param Address: 0x4019
Bytes: 3
Param Data:
0x13, 0x00, 0x00

Block Write
Time: 9:51:36 - 541ms
IC: IC 1
Param Name: IC 1.Playback Output Signal Path Registers
Param Address: 0x401C
Bytes: 14
Param Data:
0x21, 0x00, 0x41, 0x00,
0x00, 0x00, 0x01, 0xE7,
0xE7, 0x00, 0x00, 0xE5,
0x00, 0x03

Block Write
Time: 9:51:36 - 541ms
IC: IC 1
Param Name: IC 1.Converter Control Registers
Param Address: 0x4017
Bytes: 2
Param Data:
0x00, 0x00

Block Write
Time: 9:51:36 - 541ms
IC: IC 1
Param Name: IC 1.DAC Control Registers
Param Address: 0x402A
Bytes: 3
Param Data:
0x03, 0x00, 0x00

Block Write
Time: 9:51:36 - 541ms
IC: IC 1
Param Name: IC 1.Serial Port Pad Control Registers
Param Address: 0x402D
Bytes: 1
Param Data:
0xAA

Block Write
Time: 9:51:36 - 541ms
IC: IC 1
Param Name: IC 1.Communication Port Pad Control Registers
Param Address: 0x402F
Bytes: 2
Param Data:
0xAA, 0x00

Block Write
Time: 9:51:36 - 541ms
IC: IC 1
Param Name: IC 1.Jack Detect Pad Control Register
Param Address: 0x4031
Bytes: 1
Param Data:
0x08

Block Write
Time: 9:51:36 - 541ms
IC: IC 1
Param Name: IC 1.DSP ON Register
Param Address: 0x40F5
Bytes: 1
Param Data:
0x01

Block Write
Time: 9:51:36 - 541ms
IC: IC 1
Param Name: IC 1.CRC Registers
Param Address: 0x40C0
Bytes: 5
Param Data:
0x00, 0x00, 0x00, 0x00,
0x01

Block Write
Time: 9:51:36 - 541ms
IC: IC 1
Param Name: IC 1.GPIO Registers
Param Address: 0x40C6
Bytes: 4
Param Data:
0x00, 0x00, 0x00, 0x00

Block Write
Time: 9:51:36 - 551ms
IC: IC 1
Param Name: IC 1.Non Modulo Registers
Param Address: 0x40E9
Bytes: 2
Param Data:
0x0F, 0xFC

Block Write
Time: 9:51:36 - 551ms
IC: IC 1
Param Name: IC 1.Watchdog Registers
Param Address: 0x40D0
Bytes: 5
Param Data:
0x01, 0x00, 0x00, 0x00,
0x00

Block Write
Time: 9:51:36 - 551ms
IC: IC 1
Param Name: IC 1.Sampling Rate Setting Register
Param Address: 0x40EB
Bytes: 1
Param Data:
0x7F

Block Write
Time: 9:51:36 - 551ms
IC: IC 1
Param Name: IC 1.Routing Matrix Inputs Register
Param Address: 0x40F2
Bytes: 1
Param Data:
0x00

Block Write
Time: 9:51:36 - 551ms
IC: IC 1
Param Name: IC 1.Routing Matrix Outputs Register
Param Address: 0x40F3
Bytes: 1
Param Data:
0x00

Block Write
Time: 9:51:36 - 551ms
IC: IC 1
Param Name: IC 1.Serial Data Configuration Register
Param Address: 0x40F4
Bytes: 1
Param Data:
0x00

Block Write
Time: 9:51:36 - 551ms
IC: IC 1
Param Name: IC 1.DSP Slew Mode Register
Param Address: 0x40F7
Bytes: 1
Param Data:
0x00

Block Write
Time: 9:51:36 - 551ms
IC: IC 1
Param Name: IC 1.Serial Port Sample Rate Register
Param Address: 0x40F8
Bytes: 1
Param Data:
0x00

Block Write
Time: 9:51:36 - 551ms
IC: IC 1
Param Name: IC 1.Clock Enable Registers
Param Address: 0x40F9
Bytes: 2
Param Data:
0x7F, 0x03

Block Write
Time: 9:51:36 - 551ms
IC: IC 1
Param Name: Program Data
Param Address: 0x0800
Bytes: 930
Param Data:
0x00, 0x00, 0x00, 0x00, 0x00,
0xFE, 0xE0, 0x00, 0x00, 0x00,
0xFF, 0x34, 0x00, 0x00, 0x00,
0xFF, 0x2C, 0x00, 0x00, 0x00,
0xFF, 0x54, 0x00, 0x00, 0x00,
0xFF, 0x5C, 0x00, 0x00, 0x00,
0xFF, 0xF5, 0x08, 0x20, 0x00,
0xFF, 0x38, 0x00, 0x00, 0x00,
0xFF, 0x80, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00,
0xFE, 0xE8, 0x0C, 0x00, 0x00,
0xFE, 0x30, 0x00, 0xE2, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00,
0xFF, 0xE8, 0x07, 0x20, 0x08,
0x00, 0x00, 0x06, 0xA0, 0x00,
0xFF, 0xE0, 0x00, 0xC0, 0x00,
0xFF, 0x80, 0x07, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00,
0xFF, 0x00, 0x00, 0x00, 0x00,
0xFE, 0xC0, 0x22, 0x00, 0x27,
0x00, 0x00, 0x00, 0x00, 0x00,
0xFE, 0xE8, 0x1E, 0x00, 0x00,
0xFF, 0xE8, 0x01, 0x20, 0x00,
0xFF, 0xD8, 0x01, 0x03, 0x00,
0x00, 0x07, 0xC6, 0x00, 0x00,
0xFF, 0x08, 0x00, 0x00, 0x00,
0xFF, 0xF4, 0x00, 0x20, 0x00,
0xFF, 0xD8, 0x07, 0x02, 0x00,
0x00, 0x1D, 0x1F, 0x20, 0x00,
0x00, 0x0D, 0x08, 0x22, 0x00,
0x00, 0x00, 0x09, 0xA0, 0x00,
0xFF, 0xE5, 0x18, 0x22, 0x00,
0x00, 0x00, 0x08, 0xA0, 0x00,
0x00, 0x10, 0x00, 0xEA, 0x00,
0x00, 0x20, 0x00, 0xF2, 0x00,
0x00, 0x10, 0x00, 0xC0, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00,
0xFF, 0xEC, 0x01, 0x21, 0x00,
0x00, 0x04, 0x00, 0xA1, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00,
0xFF, 0xE5, 0x08, 0x22, 0x40,
0x00, 0x28, 0x00, 0xE2, 0x00,
0x00, 0x20, 0x00, 0xC0, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x2F, 0xFF, 0x20, 0x00,
0xFF, 0xE5, 0x08, 0x22, 0x00,
0x00, 0x30, 0x00, 0xE2, 0x00,
0x00, 0x30, 0x0A, 0x20, 0x00,
0x00, 0x00, 0x00, 0xE2, 0x00,
0x00, 0x5D, 0x1F, 0x20, 0x00,
0x00, 0x4D, 0x08, 0x22, 0x00,
0x00, 0x00, 0x0C, 0xA0, 0x00,
0xFF, 0xE5, 0x18, 0x22, 0x00,
0x00, 0x00, 0x0B, 0xA0, 0x00,
0x00, 0x50, 0x00, 0xEA, 0x00,
0x00, 0x60, 0x00, 0xF2, 0x00,
0x00, 0x50, 0x00, 0xC0, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00,
0xFF, 0xEC, 0x01, 0x21, 0x00,
0x00, 0x04, 0x00, 0xA1, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00,
0xFF, 0xE5, 0x08, 0x22, 0x40,
0x00, 0x28, 0x00, 0xE2, 0x00,
0x00, 0x60, 0x00, 0xC0, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x2F, 0xFF, 0x20, 0x00,
0xFF, 0xE5, 0x08, 0x22, 0x00,
0x00, 0x30, 0x00, 0xE2, 0x00,
0x00, 0x30, 0x0D, 0x20, 0x00,
0x00, 0x40, 0x00, 0xE2, 0x00,
0xFD, 0xA5, 0x08, 0x20, 0x00,
0x00, 0x68, 0x00, 0xE2, 0x00,
0xFD, 0xAD, 0x08, 0x20, 0x00,
0x00, 0x70, 0x00, 0xE2, 0x00,
0xFF, 0xE8, 0x0E, 0x20, 0x08,
0x00, 0x80, 0x0F, 0x20, 0x00,
0xFF, 0xFD, 0x1F, 0x22, 0x00,
0x00, 0x88, 0x00, 0xF2, 0x00,
0xFF, 0xED, 0x09, 0x32, 0x40,
0xFF, 0xF5, 0x08, 0x20, 0x27,
0x00, 0x78, 0x00, 0xE2, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00,
0xFF, 0xE8, 0x10, 0x20, 0x00,
0x00, 0xD8, 0x00, 0xE2, 0x00,
0x00, 0x05, 0x08, 0x20, 0x00,
0x00, 0xA0, 0x00, 0xE2, 0x00,
0x00, 0x45, 0x08, 0x20, 0x00,
0x00, 0xB8, 0x00, 0xE2, 0x00,
0x00, 0x6D, 0x08, 0x20, 0x00,
0x00, 0xA8, 0x00, 0xE2, 0x00,
0x00, 0x75, 0x08, 0x20, 0x00,
0x00, 0xC0, 0x00, 0xE2, 0x00,
0x00, 0x7D, 0x08, 0x20, 0x00,
0x00, 0xB0, 0x00, 0xE2, 0x00,
0x00, 0x7D, 0x08, 0x20, 0x00,
0x00, 0xC8, 0x00, 0xE2, 0x00,
0xFF, 0xF5, 0x08, 0x20, 0x00,
0x01, 0x30, 0x00, 0xE2, 0x00,
0x00, 0xD5, 0x08, 0x20, 0x00,
0x00, 0xDD, 0x08, 0x22, 0x48,
0x00, 0x00, 0x00, 0x00, 0x00,
0xFF, 0xED, 0x08, 0x20, 0x26,
0x01, 0x30, 0x00, 0xE2, 0x00,
0x00, 0xF5, 0x08, 0x20, 0x00,
0xFF, 0xED, 0x13, 0x22, 0x48,
0x00, 0xD5, 0x08, 0x20, 0x00,
0x01, 0x15, 0x08, 0x20, 0x25,
0x01, 0x18, 0x00, 0xE2, 0x00,
0x01, 0x05, 0x08, 0x20, 0x00,
0xFF, 0xED, 0x13, 0x22, 0x48,
0x00, 0xD5, 0x08, 0x20, 0x00,
0x01, 0x25, 0x08, 0x20, 0x25,
0x01, 0x28, 0x00, 0xE2, 0x00,
0x01, 0x3D, 0x08, 0x20, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00,
0x01, 0x48, 0x00, 0xF0, 0x00,
0x01, 0x4D, 0x08, 0x20, 0x00,
0xFF, 0xED, 0x13, 0x22, 0x48,
0x01, 0x35, 0x08, 0x20, 0x00,
0xFF, 0xF5, 0x08, 0x20, 0x25,
0x01, 0x30, 0x00, 0xE2, 0x00,
0x00, 0xD5, 0x08, 0x20, 0x00,
0x00, 0xD8, 0x00, 0xE2, 0x25,
0x00, 0xE5, 0x08, 0x20, 0x00,
0x00, 0xF5, 0x08, 0x22, 0x40,
0x01, 0x40, 0x00, 0xE2, 0x00,
0x00, 0xF5, 0x08, 0x20, 0x00,
0x01, 0x45, 0x14, 0x22, 0x00,
0x00, 0xF8, 0x00, 0xE2, 0x00,
0x01, 0x18, 0x00, 0xC0, 0x00,
0x00, 0x07, 0xFF, 0xA0, 0x00,
0x00, 0xF8, 0x00, 0xC0, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0xA7, 0xFF, 0x20, 0x80,
0x00, 0x90, 0x00, 0xE2, 0x00,
0x00, 0xBF, 0xFF, 0x40, 0x80,
0x00, 0x98, 0x00, 0xE4, 0x00,
0xFF, 0xED, 0x08, 0x20, 0x00,
0xFF, 0xEF, 0xFF, 0x22, 0x40,
0x01, 0x08, 0x00, 0xE2, 0x00,
0x01, 0x28, 0x00, 0xC0, 0x00,
0x00, 0x07, 0xFF, 0xA0, 0x00,
0x01, 0x08, 0x00, 0xC0, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0xA7, 0xFF, 0x20, 0x80,
0x00, 0x95, 0x08, 0x22, 0x00,
0x00, 0x90, 0x00, 0xE2, 0x00,
0x00, 0xBF, 0xFF, 0x40, 0x80,
0x00, 0x9D, 0x08, 0x44, 0x00,
0x00, 0x98, 0x00, 0xE4, 0x00,
0x00, 0xE5, 0x08, 0x20, 0x00,
0x01, 0x35, 0x08, 0x22, 0x40,
0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0xE8, 0x00, 0xF0, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00,
0x7F, 0xE0, 0x13, 0x20, 0x00,
0x7F, 0xE0, 0x12, 0x34, 0x00,
0x7F, 0xE8, 0x11, 0x22, 0x00,
0xFF, 0xD8, 0x12, 0x02, 0x00,
0xFF, 0xD8, 0x13, 0x12, 0x00,
0x00, 0x90, 0x12, 0x20, 0x00,
0x01, 0x50, 0x00, 0xE2, 0x00,
0x7F, 0xF0, 0x16, 0x20, 0x00,
0x7F, 0xF0, 0x15, 0x34, 0x00,
0x7F, 0xF8, 0x14, 0x22, 0x00,
0xFF, 0xD8, 0x15, 0x02, 0x00,
0xFF, 0xD8, 0x16, 0x12, 0x00,
0x00, 0x98, 0x15, 0x20, 0x00,
0x01, 0x58, 0x00, 0xE2, 0x00,
0x01, 0x55, 0x08, 0x20, 0x00,
0xFD, 0xB0, 0x00, 0xE2, 0x00,
0x01, 0x5D, 0x08, 0x20, 0x00,
0xFD, 0xB8, 0x00, 0xE2, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00,
0xFE, 0x30, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00,
0xFE, 0xC0, 0x0F, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00

Block Write
Time: 9:51:36 - 551ms
IC: IC 1
Param Name: Param
Param Address: 0x0000
Bytes: 92
Param Data:
0x00, 0x00, 0x0F, 0xFC,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0xFF,
0x00, 0x01, 0x55, 0x55,
0x00, 0x80, 0x00, 0x00,
0x00, 0x00, 0x00, 0xFF,
0x00, 0x01, 0x11, 0x11,
0x00, 0x80, 0x00, 0x00,
0x00, 0x80, 0x00, 0x00,
0x00, 0x05, 0x46, 0x4B,
0x00, 0x00, 0x00, 0x02,
0x00, 0x01, 0x9C, 0x86,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x01, 0x9C, 0x86,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00

Block Write
Time: 9:51:36 - 551ms
IC: IC 1
Param Name: Non Modulo RAM
Param Address: 0x1FFC
Bytes: 16
Param Data:
0x00, 0x7F, 0xF2, 0x59,
0x00, 0x00, 0x0D, 0xA7,
0x00, 0x7F, 0xF2, 0x59,
0x00, 0x00, 0x0D, 0xA7

Read Request
Time: 9:51:36 - 561ms
IC: IC 1
Param Name: IC 1.PLLCrlRegister
Param Address: 0x4002
Bytes: 6

Block Write
Time: 9:51:36 - 561ms
IC: IC 1
Param Name: IC 1.Sample Rate Setting
Param Address: 0x40EB
Bytes: 1
Param Data:
0x01

Block Write
Time: 9:51:36 - 561ms
IC: IC 1
Param Name: IC 1.DSP Run Register
Param Address: 0x40F6
Bytes: 1
Param Data:
0x01

Block Write
Time: 9:51:36 - 571ms
IC: IC 1
Param Name: IC 1.Dejitter Register Control
Param Address: 0x4036
Bytes: 1
Param Data:
0x00

Block Write
Time: 9:51:36 - 571ms
IC: IC 1
Param Name: IC 1.Dejitter Register Control
Param Address: 0x4036
Bytes: 1
Param Data:
0x03

Read Result
Time: 9:51:36 - 991ms
Param Name: IC 1.PLLCrlRegister
Param Address: 0x4002
Param Value: 0
Bytes: 6
Param Data:
0x00, 0xFD, 0x00, 0x0C,
0x20, 0x03

Audio Signal Processors

SigmaDSP Audio Processors

adau1761

Report
Yagami Reply
May 7, 2014 00:00

Hello,

I have some experience with the ADAU1761, so let me try to answer your questions.

1) What is the minimum delay time required for the PLL to settle assuming good
quality MCLK input? Is this characterized?

This appears to not be characterized. Only a maximum time is specified in the datasheet. To me, this signifies that the PLL lock bit must be used as an indicator to see if the PLL has achieved lock or not.

Regarding the SigmaStudio capture window contents below:

2) The data sheet indicates no register access should occur during PLL
configuration until 'LOCK' is verified. We then assume the 10ms "DELAY" must be
sufficient to insure PLL Lock. Is this true?

It seems that the PLL should take less than 10 ms to lock in integer mode. I'm not sure if the fractional PLL takes longer to lock - typically, it does. I think the designer at ADI would have to comment about this.

3) Near the end of the sequence a PLLCrlRegister read request appears to return
no data. Why is no data returned? Why is this read request issued at this point
in the sequence?

Actually, the result comes later. In fact, your question 3 is answered in your question 4...

4) The final operation again reads the PLLCrlRegister. This time valid data is
returned indicated 'LOCK'. What is the purpose of this final PLLCrlRegister
read?

The SigmaStudio capture window denotes that SigmaStudio is attempting to read from the hardware by labeling the line "Read Request". Sometimes, it then goes and does some other writes before displaying the result, "Read Result".

Of course, in the hardware, this read happens immediately. However, I assume that this is simply an artifact with the way SigmaStudio handles the data and displays it.

You can test this by using a DSP Readback cell to manually read back memory addresses. When you execute a read, you'll see a Read Request followed by a Read Result in the capture window.

I don't think there's any real necessity for this last read of the PLL control register. Perhaps SigmaStudio is just double-checking that the PLL is locked for good measure. I don't think this is necessary in a production system.

Hopefully somebody at ADI can confirm my understanding... but in the meantime, hopefully this will be helpful to you!

Report
ADIApproved Reply
May 7, 2014 00:00

Thanks Yagami. This is good feedback. It turns out the PLL 'Lock' was detected properly. The issue had more to to do with allowing some time for things to configure before accessing the 1761. We were able to get things going this morning. -Phil

Report