Chip damage from IOVDD low while I2C active?

I should also point out that the USBi board holds SCA/SCL "sort of" high when the host PCB (with SigmaDSP) power is shut down, to about 1.3V (in my circuit), and this creates about 1V to IOVDD due to other loading on that power net. Per the spec (Table 8), this is right on the edge of the maximum allowed rating. This might present a problem for some people whose circuit may pull IOVDD lower than this; a diode might be a good recommendation.

Hi joe42,

The internal diodes that are designed to prevent the IC from being damaged in case of EOS (electrical overstress) are referenced to IOVDD. Therefore, if IOVDD is grounded and a digital pin on the device is being held to a voltage significantly higher than IOVDD, it's possible that internal damage could occur because the protection diodes are not functioning correctly.

SDA/SCL are exceptions to the rule because they are not strictly digital I/O pins. Both SDA and SCL are bidirectional and internally I think they are open collector in the case when they are outputs, which means that they probably wouldn't be subject to the same damage conditions as pins that are strictly digital I/O.

I think in general you want to design the system such that any devices that interface digitally with the ADAU1701 will release their lines when the ADAU1701's IOVDD power is removed.

Thanks for the detailed response. My immediate goal is to have confidence that the SigmaDSP failures I've seen are due to voltage being present on SDA/SCL while IOVDD is low... mostly so I can stop searching for other problems. Your response, that this shouldn't be an issue, doesn't give me the confidence that this is what is causing my chips to fail. How certain are you that this shouldn't cause damage? The most recent failure I saw was specifically when IOVDD was powered down with I2C (on the microcontroller) still active.

In any case, it's certainly good practice to ensure that this state doesn't occur. However, this seems to be an unusual restriction for IC's in general, so it's good to give it a bit more attention.

Hi joe42,

I'm sorry - when I go back and read my previous post, it's clear that it's a bit misleading.

When I said that SDA and SCL wouldn't be subject to the same damage conditions as pins that are strictly digital I/O, I didn't mean to say that damage wouldn't be caused on these pins in your scenario - I was simply trying to say that the internal circuit for those two pins is special and differs from standard I/O pins.

That being said, it's possible that they have the same ESD/EOS protection diode circuit internally and that would pretty much render my previous comment useless. In that case, driving the pin without powering IOVDD would cause the diode to conduct current, and that could damage the device if that condition is held for a period of time.

I think this issue can only be answered by somebody with more detailed knowledge of the inner workings of the device. The key point here is that driving pins on any IC when it is not powered up is generally going to set up the potential for damage. I wouldn't be surprised if your assumption is correct and this is indeed the cause of the failures you are seeing.

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Thank you,
EZ Admin