ADAU1701 multiplier and accumulator infos
Hi everybody. I'd need to know how a FIR filtering works. From datasheet I read that:
multiplier have 28x28 bits and I suppose 56bits output, right? Is the 56bits output also for FIR filtering?
accumulator have 56bits but in full precision mode, for FIR filters is the same, since FIR filtering works in signle precision?
Knowing these infos I can decode the entity of round and roundoff error for FIR filtering having high taps.
I hope you can help me.
Regards, Leo.
Audio Signal Processors
filter
sigmastudio
SigmaDSP Audio Processors
adau1701
Hi Leo,
The experiment below has a slow, full-throttle sine wave driving a FIR filter set up as a differentiator (two full-scale, opposite polarity taps). Its clean output shows that the coefficient x data multiplications can produce outputs approaching + and - 256. Here these nearly cancel out, resulting in the much smaller output.
The same differentiator made with discrete delay, gains and adder doesn't work, showing that the FIR filter has been set up in some special way to handle the results of full-scale multiplies. I assume the accumulated sum as each tap is added must always remain within the 5.23 format, since that's all that the filter can output. I haven't figured out a way to test the filter's precision, so hopefully someone from ADI will shed additional light on your question.
Best regards,
Bob
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Thank you,
EZ Admin
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