S/PDIF-only on ADAU1446, what clock enable bits?

Hi Dany,

I think you will also need to set bit [1] to activate the serial inputs. It's just a nomenclature thing, but this bit really means "Activate the serial audio data inputs to the DSP core". The S/PDIF receiver signal goes through a conversion to standard PCM serial data and is then input to the core, so if bit [1] is not set, then the data will not get through.

Funny enough, bit [2], which controls the serial outputs, is not necessary for using the S/PDIF transmitter. This is because of the way that the signal is routed from the output of the DSP to a memory map and then on to the S/PDIF transmitter.

So, your settings would have to be:

There is one important thing to note about using the ADAU1446's S/PDIF Receiver. The datasheet makes a small mention of this on page 65, but it is actually quite important: "Because the S/PDIF input data will most likely be asynchronous to the DSP core, it must be routed through an ASRC."

If you think about it, the S/PDIF receiver is a slave to an external signal with an embedded clock. In most systems, that S/PDIF signal is coming from off-board. That means there is very little chance that the source of the S/PDIF signal is using the same master clock source as the ADAU1446, which means that the two will be asynchronous.

Even if the S/PDIF signal is at 48 kHz and the SigmaDSP is getting a 12.288 MHz clock (or some other integer multiple of 48 kHz), the reality is that the two domains will not be exactly frequency locked. Perhaps the S/PDIF signal will be running at 48.0001 kHz and the SigmaDSP will be at 47.9999 kHz. This means you would get an audio glitch at a frequency of 0.2 Hz, or once every five seconds.

The only way that this would work is if you are certain that the S/PDIF signal's source is clocked from the exact same MCLK signal as the SigmaDSP itself, which would make them synchronous.

If that's not the case, then an ASRC would be required. This would require an ADAU1445 or ADAU1442 in the system.

Hello,

Thanks for all the research, and share your experience with me.

Actually, my goal was to concentrate the processing of my two ADAU1761 (other messages in another discussion) by using the much larger program memory of the ADAU1446. The only thing is that this chip consumes a good amount of current, and for a portable device, I was attemting to limit the current, by cutting all the "unnecessary" clocks. I thougth of using the ADAV803 or NXP's UDA1355H, the only Codecs I found with an S/PDIF interface. Yes they would have been neighbours and would have used the same master clock.

I see I need to think again about my scheme, especially since the project is very advanced with the two '1761s.

Best regards

Dany