ADAU1761 I2S TDM8 Interface with ADV7611
I have a design that interfaces an ADV7611 HDMI Receiver with an ADAU1761 SigmaDSP processor. My DSP is current just passing through the first 2 digital channels to the DACs for debug. I got the design working in I2S mode with stereo data without a problem. In my final design I want to be able to use the TDM8 mode out of the ADV7611 to get 5.1 channel audio processed by the ADAU1761. While testing this scenario I have not been able to get this working with the expected setup.
I am using a 48KHz sampling rate out of the ADV7611 and I have verified that I am receiving 256 samples per frame and the MCLK from the ADV7611 is 12.288MHz. I’ve attached an image showing the setup for the codec and the digital interface from SigmaDSP as well as an oscilloscope trace showing the TDM stream going to the ADAU1761.
In trying to figure out how to get this to work, I happened to place the ADAU1761 in SDATA “MASTER” mode which caused contention on the LRCLK and BCLK lines, but did allow the audio to pass through correctly. This did not work consistently through power cycles and is obviously not a good idea, but for some reason it did work sometimes.
Audio Signal Processors
adv7611
HDMI/DVI Receivers
i2s
tdm8
SigmaDSP Audio Processors
adau1761
HDMI/DVI Devices
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Here's a link that describes how the serial port channels are mapped for TDM8 mode. It may be possible the data is not showing up in the slots you expect?
I have verified the TDM8 mapping and also tried all 8 digital channels that are available and all with the same result. The audio coming out of the DACs is an intermittent popping sound. By switching the polarity of the BCLK I can get consistent loud static that sounds like it is mixed with the audio from the disc, but the data is obviously transitioning on the falling edge of BCLK.
In your setup for the 1761 it looks like you are expecting left justified audio as the Data Delay LRCLK edge is set to 0. In the ADV7611 datasheet it states that the audio is output in I2S mode in TDM (audio delayed by 1 bclk). Can you confirm the data format expected is the same for both chips?
You are correct this is supposed to be I2S mode and should have a 1 clock delay. I have tested with all possible options for the data delay setting with no success. In my standard setup that I am running I am using the 1 clock delay which I believe corresponds to the incoming data snapshot as shown in my original post.
Shane
Is it possible to make the ADV7611 a slave and the 1761 the master so as there is no contention on the lines? If it worked consistently with the ADAU1761 as master there maybe some kind of timing issue.
Unfortunately, the ADV7611 does not allow running in slave mode. I'm looking at the possibility of a skew issue on the LRCLK right now because if I probe just the LRCLK, the audio goes silent and if I probe both LRCLK and BCLK I get the exact same behavior as with no probes. Probes are 8.0pF.
I found the solution to this issue. Based on Figure 57 from the ADAU1761 datasheet I added a 47pF capacitor between LRCLK and ground which apparently gives it enough of a shift to consistently align after the rising edge of the BCLK. The datasheet only requires this capacitor when using LRCLK in Pulse mode which I am not doing, but clearly from the oscilloscope trace the LRCLK is being aligned way too close to the rising edge of BCLK.
I believe this is a problem with the ADV7611's I2S driver in TDM mode as it looks like the LRCLK is actually being driven on the wrong edge of the BCLK and there is no control for this in the part itself. Regardless, with the added capacitor it is now working consistently and I can move on with the project.
This question has been closed by the EZ team and is assumed answered.
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