ADAU1701 Clocking and PLL

Hi JeradL,

thanks for your response which helps a bit but still leaves some open questions.

I´ve read the manual on page 16 but it´s for me not quite precise there. In the section 'setting master clock/pll mode' there is not mentioned that the fs has to be 48 kHz or I missed it.

If the PLL setting is bound to a specific MCLK it would be more obviously to give the configuration settings for a specific MCLK (12.288 MHz) rather then for a sampling frequency and a muliplier (64 x fs), like if your clock is 24.576 MHz PPL mode pins have to be that value. Above all if there is a '512 x fs' and there is a setting of 512 instructions in the DSP core reg. At least for me this gives room for misinterpretation.

Back to the problem: As mentioned before, my MCLK is 24.576 MHz and the PLL mode pins are hardcoded to 256. What can I expect to happen with the sigmaDSP? Will it work? From what you wrote this should yield to a double internal clock which sounds to me a bit high to work properly!

Just to see if I got it right now: The clock flow is then as follows: The MCLK is divided down to generate a sampling frequency of 48 kHz (and only 48 KHz). This fs is internally increased to 49.152 MHz core clock. This clock can be increased by changing the values in the DSPCoreregister. A higher clock (e.g. 96 KHz) affects the whole signal processing and the serial audio outputs are reflecting this clock too.

The MCLK and the PLL settings have to be chosen that way, that sample freq is always 48 kHz.

best,

rastariot

The ADAU1701's PLL should always be set to generate a 1024 x fs core clock for a typical 48 kHz sample rate (49.152 MHz, assuming fs = 48 kHz). If your system's sample rate is 96 kHz, then the multiplier will be 512 x fs. This is described on page 16 of the datasheet under the heading "Setting Master Clock/PLL Mode." If your input clock is 24.576 MHz, then you need to set the PLL pins to the 512*fs settings (PLL_MODE0 = PLL_MODE1 = 1).

This FAQ shows examples of how to set the sample rates for different SigmaDSP processors. The sample rate setting at the top of the SigmaStudio window is used for calculating filter coefficients; it is not controlling a hardware setting. You should set the sample rate in this drop-down box to match your hardware sample rate settings.

This thread might help to clear up some confusion.

Just to be clear, the core is always running at 49.152 MHz, but in the case of dual-rate or quad-rate processing, you're simply ordering the DSP to output a sample and grab a new input sample at twice or four times the rate, respectively. So, the clocks inside the device don't really scale up or down by changing the core sample rate - the data is simply latched in and out at a multiple rate.

Also, to be complete, it's worth noting that the core doesn't have to be run at 49.152 MHz (for sample rates of 48 kHz, 96 kHz, or 192 kHz). You could also scale the input MCLK down and run the core at 45.1584 MHz (for sample rates of 44.1 kHz, 88.2 kHz, or 176.4 kHz).

This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

Thank you,
EZ Admin