ADAU1701: working at 96Khz

Hello,

1. We typically use the selfboot function with a 1 MHz EEPROM as on the evaluation board, but any EEPROM that meets the size requirements and has sufficient speed should work.

2. Please use 12.288 MHz in this case.

3. Please set the PLL pins for 256 mode (as you would normally in 48 kHz mode).

4. The number of available MIPS will be cut in half. Instead of 1024 instructions, you will only be able to use 512 instructions. The total number of instructions used will appear in an output file - compiler_output.txt - which can be found in the project's directory after compilation.

The reason why you should leave the XTAL frequency and PLL mode the same as you would in 48 kHz is that all of the internal clocks will be actually running at the same rate. We simply double the rate of the sample clock in the DSP core and the serial ports (of course, in the serial ports the BCLK rate is also doubled). The logic is that most customers use the ADAU1701 at 48 or 44.1 kHz, and therefore we designed the system to run at its maximum allowable rate (using the common 12.288 MHz crystal frequency) at these sample rates. By doubling or quadrupling the core rate (thereby halving or quartering the allowable instructions), higher sample rates are allowed.

Thanks a lot.

1: Ok, I will use a 1Mhz I2C EEPROM

2,3: I've tried with a 12.288Mhz xtal, setting PLL pins for 48Khz, and setting 96khz in Sigmastudio but I'm not able to obtain an effective computational 96khz sampling rate (DSP program works properly also using 1024 instruction per sample)

Using a 24.574Mhz XTAL all worls ok (only 512 instruction are allowed and I measure an effective 40Khz bandwith).

Do you confirm that a 24.574Mhz XTAL is not usable with ADAU1701?

4: Ok, I've noted the file.

Hi Brett.

Today I made more tests with ADAU1701 and selfboot at 96khz.

I want to start by saying that:

- I've used a fast EEPROM (24FC128)

- I've used a 24.574 XTAL beacause in the datasheet (page 15, table 11, Power up time) is given the powerup time with an MCLKI input frequency of 24.576Mhz. So I assume that 24.576Mhz is a valid frequency for MCLKI.

- Using Link-compile-download my application works properly at 96Khz

- PLL_CONFIG pin are correctly configured for working at 96khz with an XTAL of 24.576

- In SigmaStudio project, in Hardware Configuration form, I've correctly set "program Lenght" to "2x 512 Instruction) as required for propery working at 96khz.

- If I program and verify EEPROM with sigmastudio and then restart the DSP, selfboot doesn't work (with the same circuit and program, at 48khz it work)

I noticed the following points:

- 1: Monitoring SCL pin during selfboot I've noted that the SCL frequency of selfboot isn't 768khz (96khz*8, by datasheet SamplingFreq*8) but is 384khz (48Khz*8).

- 2: After selfboot I've readed some DSP register using an I2C debugging tool.

I've noted that all register are configured properly (as selected in my sigmastudio program) but DSP doesn't output any audio signal.

On DSP CORE CONTROL REGISTER 0x081C the SR bits are readed as 00 (1024 Instruction that is correct for 48khz SR) instead of 01 (512 Instruction that is correct for 96khz SR).

If I manually write 01 in SR bits the DSP start to working properly.

It therefore seems that at 96khz selfboot is effectively done, but SR bits in DSP core control register are incorrectly configured for 48khz.

It's possible that the selfboot eprom file generated by sigmastudio doesn't properly set the SR bit for 96Khz?

I encountered a similar problem with the selfboot of adau1446 and the problem was solved with the latest sigma studio release.

Link of the discussion: https://ez.analog.com/thread/1646?start=0&tstart=0

The base sample rate of the device, which is used by the ADCs, DACs, and PLL, is called Fs. The ADAU1701’s design was based around the concept that Fs should equal either 48 kHz or 44.1 kHz. A control register allows the DSP core and serial ports to run at 2 x Fs or 4 x Fs, independently of all other functional blocks in the system. So, even when running the serial ports and core at double or quadruple rates, the frequencies of other clocks in the system, notably the MCLK input, should not change from their values when the core and serial ports are running at the normal base rate.

Therefore, there are four choices for the PLL configuration and master clock frequency of your 96 kHz system:
Input MCLK in 64 x Fs PLL mode is 3.072MHz
Input MCLK in 256 x Fs PLL mode is 12.288 MHz
Input MCLK in 384 x Fs PLL mode is 18.432 MHz
Input MCLK in 512 x Fs PLL mode is 24.576 MHz

Remember, Fs in these cases equals 48 kHz, or the "base" sample rate.

In all cases, you need to configure the core to run in double (96 kHz) mode. Essentially, the core is running at double the base rate.

For the ADAU1701’s PLL, we do explain this in the datasheet. On page 16, there is a paragraph that explains the table of PLL modes is for 48 kHz and that these multipliers will be cut in half (or quartered) if running the part in dual or quad speed modes.

Thanks for your comment about the selfboot causing an issue at 96 kHz mode. I'll look into how that register's value is being saved in the EEPROM. Perhaps it's simply not being loaded with the proper value - I'll ty to figure this out!

Ok, now it is clear

Thanks a lot for your very comprehensive explanation.

Hello,

to be sure that I understood, if I use an oscillator at 24.576 MHz on MCLKI (I need that frequency for a Class D amp - TAS5010), and if I put PLL_MOD0 PLL_MOD1 to 1, I have well functioning correct with a 192KHz sampling rate?

thanks a lot

Setting PLL_MODE1 and PLL_MODE0 to 1 will set the PLL for a 512 x Fs rate, which is 24.576 MHz. So yes, this is correct.

You also need to make sure to follow these steps to make sure your SigmaDSP is set to run a quad rate (192 kHz).

ok, thanks