ADAU1761 I2S

I'm not sure I'm clear on what your synchronization concern is. Are you asking about when the first data word will be output from the serial port? The clocks and data output will be enabled as soon as you set the ADAU1761 into master mode. This is not guaranteed to happen at the beginning of an LRCLK frame (LRCLK falling edge for I2S mode). Within an I2S data frame, the left and right channels will always be synchronized, meaning that there is no delay between the channels introduced in the serial ports.

Please feel free to clarify your original question if I haven't answered it sufficiently.

Hi JeradL,

my problem is the following:

I have a microcontroller programmed in I2S slave mode that receive the audio stream.

In order to works properly the I2S interface of the microcontroller has to be configure as following:

The transmission sequence begins when the external master device sends the clock and
when the LRCLK signal requests the transfer of data (LRCLK assertion corresponds to left channel transmitted
first).

The slave has to be enabled before the external master starts the communication.

At a certain time I need to stop the I2S... I tought was sufficiento to disable the codec but,

for what I understand, in order to keep the correct synchronization I need to monitoring the LRCLK pin.

Thanks for the explanation.

Sorry that I'm still not understanding. If you disable (power-down) the ADAU1761, the serial port clocks will of course stop being output. The line in your last post I'm still confused about is the last one:

...for what I understand, in order to keep the correct synchronization I need to monitoring the LRCLK pin.

What is it that you're monitoring on LRCLK, and what synchronization is this affecting? Are you talking about inter-channel synchronization, such as between right and left channels, or inter-IC synchronization between the two ICs?

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Thank you,
EZ Admin