SigmaDSP generated include files for ADAU1761

I have a second question:

I found in the download sequence the following istruction:

SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_CODEC, REG_DEJITTER_REGISTER_CONTROL_ADDR, REG_DEJITTER_REGISTER_CONTROL_BYTE, (u8*)R32_DEJITTER_REGISTER_CONTROL_Default );
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_CODEC, REG_DEJITTER_REGISTER_CONTROL_ADDR, REG_DEJITTER_REGISTER_CONTROL_BYTE, (u8*)R33_DEJITTER_REGISTER_CONTROL_Default );

I didn't find any reference of REG_DEJITEER in the datasheet ( register 0x4036 )

What is the meaning of this new register?

Hi Stefano,

The De-Jitter window register is new and it will be updated in the next release (Rev. B) of the datasheet. It needs to be toggled when you download your program to the ADAU1761. For now, simply follow the sequence given by the SigmaStudio output files.

To answer your first question...

The first two instructions basically shut down the core before the download occurs. These are included in case the DSP is already running when you perform the download sequence. It's necessary to mute the core in order to avoid errors on the DACs or serial output ports.

Regarding the exported function default_download().....

Shouldn't there be a wait/check for PLL lock immediately following the write to the PLL register?!

What guarantee do we have that the subsequent register, program ram, and parameter ram writes won't violate timing due to the PLL overclocking while it settles?

I am assuming that these register and memory blocks are using the DSP core clock - is that true?

If this is the case, then perhaps another user-defineable macro should be inserted for this purpose directly after the PLL register write....

Hi Bob,

Yes, I agree with you there. I actually checked with the software team and they've already taken this into consideration and implemented it on the internal debug version of SigmaStudio. You can see the wait command inserted into the download sequence below:

I am told this will make it into the next release of SigmaStudio.

Hi Bob,

in the init sequence I'm using this piece of code:

// set PLL
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_CODEC_MON, REG_PLLCRLREGISTER_ADDR, REG_PLLCRLREGISTER_BYTE, (u8*)R3_PLLCRLREGISTER_Default );

// wait PLL lock

registro[5] = 0;
loop = 0;
while( (registro[5] & 0x02) == 0) // check PLL lock bit
{
loop++;
if (loop > 1000)
{

DeviceStatus.errore = ERRORE_CODEC2;

return;

}

SIGMA_READ_REGISTER(DEVICE_ADDR_CODEC_MON, REG_PLLCRLREGISTER_ADDR, registro, 6);
Delay(5);

}

// CLK ENABLE
registro[0] = 0x7F;
registro[1] = 0x03;
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_CODEC_MON, REG_CLOCK_ENABLE_REG_0_ADDR, 2, registro );

A constant delay could be enought but I prefear to check the PLL LOCK bit ....

inventis,

I do the same. I insert a function to wait for DSP lock Immediately after the write to the PLL register. in the default_download() function. Then, it proceeds to write the rest of the registers, program ram, and data ram. The problem with this, of course, is after making changes to the DSP code, I have to modify the default_download() code each time....

Eventually, I'll need to create my own function that allows for write/read_verification of memory before running.

One question I have - will the PLL go in and out of lock as it settles, or does the PLL flag signify that the PLL has settled and is finally locked?

Do we need to wait a bit longer after the first lock? Is that why there is a wait delay added to SigmaStudio?

bobw wrote:

One question I have - will the PLL go in and out of lock as it settles, or does the PLL flag signify that the PLL has settled and is finally locked?

Do we need to wait a bit longer after the first lock? Is that why there is a wait delay added to SigmaStudio?

With a stable input clock, once the PLL has locked it should not unlock. The lock flag going high indicates that the PLL is in its locked state and it should not unlock unless the input clock changes or has excessive jitter. The wait delay is used in SigmaStudio in lieu of polling the lock bit to wait for it to be set to 1.

The delay feature is included in the newly-available beta version of SigmaStudio. Please see this thread for additional details.

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Thank you,
EZ Admin