ADAU1446, SERIAL_OUT management

Hello,

I'm using ADAU1446, and I use 4 outputs whith TDM2, I2S signals. They all share the same bit clock.

They are put on SDATA_OUT0,SDATA_OUT1,SDATA_OUT2,SDATA_OUT3

So I output clock, master, fs normal for SDATA_OUT2 on LRCLK11 and BCLK11. So far so good.

Register 0xE042, master, clock is fS,NORMAL and Clock output enable

But for 3 other data, what config should I set ?

I have try "slave to Clock Domain 11". But it doesn't work, no data outputed on SDATA_OUT0,1,3

Should I configure master, clock is fS,NORMAL, without Clock output Enable ? It seems the good solution, but datasheet say this (p43) :

>Clock Domain Master/Slave Select Bits (Bits[13:10])
>These bits set whether the serial port outputs its clocks as a master or slave to an available clock domain. If a serial port is set to be a master, the clock >output enable bit (Bit 15) must be set to 1. If a serial port is set as a slave, the clock output enable bit (Bit 15) must be set to 0. In both cases, the >corresponding clock pad multiplexer must be set to the serial output domain, if assignable. For more information, see the Clock Pad Multiplexer section. >Note that an arbitrary number of serial ports can be slaves to a single clock domain, but a single serial port can only be a master to one clock domain. >The values for fS,NORMAL, fS,DUAL, and fS,QUAD are 48 kHz, 96 kHz, and 192 kHz, respectively, for a 172.032 MHz core clock signal.

So config with master and no output seem to be not legitimate ?

Thanks for answer !

Audio Signal Processors

adau1446

SigmaDSP Audio Processors