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ADAU1761 PLL lock

SigmaDSP & SigmaStudio farhad20 Dec 10, 2009 00:00 3 replies Original on forum ↗
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farhad20 Question
Dec 10, 2009 00:00

Hello

I am not able to see Lock bit in PLL control register (ox4002) changes from 0=>1 during initilization of ADU1761.

If I skip checking this flag it seems DSP is running fine.

Here is my code:

void Init_ADAU1761(void) //to test by-pass DSP
{

ADAU1761_pll_locked=0;

ADAU1761_SAMPLERATE_SET_REG(0x7f); //ok
ADAU1761_DSP_RUN_REG (0x00); //0k
ADAU1761_CLOCK_CONTROL_REG (0x0f);//ok
ADAU1761_PLL_CONTROL_REG(0x00,0xfd,0x00,0x00,0x20,0x03); ///<<--???
ADU1761_SERIALPORT_CONTROL(0x00, 0x00);
ADAU1761_ALC_CONTROL_REG (0x00,0x00,0x00,0x00);
ADAU1761_MIC_CONTROL_REG(0x00);

ADAU1761_RECORD_IN_SIG_PATH_REG ( 0x00, 0x51, 0x00, 0x51,
0x00, 0x44, 0x5e, 0x00 );
ADAU1761_ADC_CONTROL_REG ( 0x33, 0x00, 0x00); //<- 20 Nov 2009 changed to turn on HP of ADC (0x13,0x00,0x00);
ADAU1761_PLAYBACK_OUT_SIG_PATH_REG ( 0x21, 0x00, 0x41, 0x00,
0x03, 0x09, 0x01, 0x01,
0x01, 0xfe, 0xfe, 0x01,
0x00, 0x03);

ADAU1761_CONVERTER_CONTROL_REG(0x00,0x00);
ADAU1761_DAC_CONTROL_REG(0x07,0x00,0x00); //enable DAC de-emphasis (0x03,0x00,0x00);

ADU1761_SERIALPORT_PAD_CONTROL(0xaa);
ADU1761_COMMPORT_PAD_CONTROL (0xaa,0x00);
ADAU1761_MCLK_JACKDET_PAD_CONTROL_REG(0x0a);

ADAU1761_DSP_ON_REG(0x01);
ADAU1761_CRC_REG(0x00,0x00,0x00,0x00,0x01);

ADAU1761_GPIO_REG(0x00,0x00,0x00,0x00);
// ADAU1761_NON_MODULO_REG(0x0f,0xfe);
ADAU1761_WATCHDOG_REG(0x01,0x00,0x00,0x00,0x00);
ADAU1761_SAMPLERATE_SET_REG(0x7f);

ADAU1761_ROUTING_MATRIX_IN_REG(0x00);
ADAU1761_ROUTING_MATRIX_OUT_REG(0x00);

ADAU1761_SERIAL_DATA_CONFIG_REG(0x00);
ADAU1761_DSP_SLEW_MODE_REG(0x00);
ADAU1761_SERIAL_PORT_SAMPLERATE_REG(0x00);
ADAU1761_CLOCK_ENABLE_REG(0x7f,0x03);

ADAU1761_PROGRAM_DATA_WRITE(); // <- note debug it!!
ADAU1761_PARAM_DATA_WRITE(); // <-note debug it!!

// ADAU1761_NON_MODULO_RAM();
//ADAU1761_PLL_CONTROL_REG() //READ REQUEST
//ADAU1761_DSP_ON_REG(0x01);

ADAU1761_pll_locked=0;
while ( ADAU1761_pll_locked == 0x00 ) // interrupt ISR updates this flag {
Delay_100();// for (i=0 ;i<10 ;i++) {for (j=0; j<10 ;j++) {} }
ADAU1761_PLL_Control_Read();
}
ADAU1761_DSP_RUN_REG(0x01);
ADAU1761_SAMPLERATE_SET_REG(0x01);

}

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ADIApproved Reply
Dec 10, 2009 00:00

Farhad,

Are you reading anything from the PLL Control register (0x4002)? A read from that register will output all six bytes. The PLL lock status bit will be the LSB-1 bit of the last byte. Are you able to read from other registers after you write to them?

farhad20 Reply
Dec 11, 2009 00:00

Thanks Jerad , I was looking at Byte#0 instead of Byte#5.

I think table 35 in ADAU1761 data sheet should be reversed to have Byte#5 at top.

BR,

Farhad

EZAdministrator Reply
Aug 2, 2018 00:00

This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

Thank you,
EZ Admin