Can I use the ADAU144x as a clock master for an asynchronous clock domain?

No.

The ADAU144x has a very flexible clock domain system, but it can only generate clocks (that is, be a serial port master) at multiples of the base internal sample rate. In the datasheet, the internal core sample rate is referred to as fCORE. Serial ports can only be masters at rates equal to fCORE, fCORE,DUAL, and fCORE,QUAD (fCORE times 1, 2, and 4).

For example, if fCORE was 48 kHz, a serial port could be a master for (snychronous) 48 kHz, 96 kHz, and 192 kHz clock domains.

So, the ADAU144x cannot be used as an asynchronous clock buffer. The best way to output asynchronous signals is to route the asynchronous clocks to an output-side clock domain pin pair and set up a serial output port to be a slave to that pin pair. In this case, the corresponding ASRC's target rate must be set to the corresponding serial output port.

This question has been closed by the EZ team and is assumed answered.