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Q&A from Analog Devices EngineerZone: SigmaDSP/SigmaStudio and DSP discussions (52 topics).
52 topics · 226 messages
Filtered by: #delay ✕
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Does SigmaDSP perform SCLK stretching for timing sync with USBi?
After some reliability issues with SigmaStudio ReadBack (both EVAL and custom hardware, alike), I am looking at the USBi bus in SPI mode with a logic analyzer, and it appears that the SigmaDSP might b
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Runtime Delay Adjustment Causing Unexpected Glitch in SigmaStudio 4.5
I'm using multiple simple Delay blocks to offset separate data flows in a SigmaStudio 4.5 project. ___________________________________________ Example Setup: SourceA --> DelayA --> SourceA_delayed Sou
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Fractional Delay Buffer Splitting Problem
When I create a project and use two fractional delay blocks that sample the same signal, the compiler shows that buffer space is reserved only once—which seems logical. I want to use 48 fractional del
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Audio Delay versus Sample Rate
When operating the ADAU 1701 with double to fourfold sample rate the audio delay (analoge input to analog output) is not 1/2 or 1/4 compared to 48 kSps as expected. I measure 1/3 and 1/9 compared to 4
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External SPI Delay with SRAM
Dear, We use the ADAU1467 and have need a audio delay of more than 1 sec for at least 8 channels (max 12 channels). The sample rate is 48Khz at 24 bits. I will have a rate of 48Khz sps * 24 bit * 12 =
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External SPI Delay on multiple channels shared with SRAM?
Dear ADI community, I'm currently planning to build an algorithm/architecture for the ADAU1466 where each of 8 outputs gets the option to set up to pretty high delay at 96 kHz (up to 1 second per chan
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Delay problems 1701 DAKB4100
Hi guys. Im new to using the SigmaDSP and I am using with the Dayton Audio KABD 4100 board which uses the 1701 DSP. And i am having huge trouble with the delay function. I understand that the only way
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i2s delay chain from input to output
Hi, in these days I'm testing the ADAU 1761 codec connected in I2S with an FPGA that generates the stimulus signals in order to check the behaviour of ADAU. The FPGA genearate a I2S toward the ADAU wo
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SigmaStudio+
A delay of 500ms is required, divided into DM0 and DM1 blocks, but the total is still not more than 20480. But SigmaStudio software is OK. Audio Signal Processors adau1452 Audio Products software Sigm
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Pin output sequence for power on and shut-down amplifier section
Hi guys. I would like to make a logical sequence to turn on the amplifier section with my 1701s. When I generate the start pulse (I use the encoder button) I need two outputs. The first output goes hi
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How to increase Delay time?
Hello Forum Users, Delay time is often at a premium and being able to use it more efficiently is a good thing. The question is how do I more efficiently use delay memory? The memory is 32 bits but 32b
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How to implement external control using a rotary encoder to a DSP that does not have any type of external control on the ADAU1701 chip
Hello, I am creating a signal delay device for PA systems. For this I am using the DSP Delay that comes with Signa Studio and I need to add physical control using a rotary encoder but in the delay I c
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Miscellaneous click and pops with delay block
I have been tyring to implement a simple chorus effect on the ADAU1701 using a voltage-controlled fractional delay, and a couple of sinusoidal oscillators. When I download and run the attached SigmaDS
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ADAU1452 spi extern delay module do not work
I use SPI SRAM (23LC1024) connected to the master spi interface of 1452, and test the sigma studio module. But I found that it do not work well. the audio playing back is not right. the sigma studio p
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Multi-Tap Voltage Controlled Delay Maximum number of samples compiler error
Hello team, I have a simple project (attached test project) in which I have 8 channels with 8 delays of the type "Multi-Tap Voltage Controlled Delay". To make the most of the available memory I have 3
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SigmaStudio Python scripting - Change delay value
Hello I have been developing a python wrapper to go around an existing sigmastudio project and we are having trouble with changing the delay value via python script. Every other value we are successfu
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ADAU1452 multiple instances of External Delay block
Hi to all, I need to implement a 4IN - 8OUT processor on ADAU1452 and I need to manage 4 long delay cells, one for each input channel, with different values on each. The RAM inside ADAU1452 is not eno
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External SPI delay for long delays
Hello, I have a PCBA with an ADAU1401 performing some ADC-DSP-DAC tasks and it works pretty fine. now I need to add a big delay to the audio, so I came to the possible solution of codec+DSP. I am tryi
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ADAU1452 SPI RAM
HI team. So I bought Adau1452 custom board from China, I am sure this board is common for now. Most of the function is normal. selfboot is also normal. No problem so far. But, I want to do the SPI del
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-- How to have a long delay with ADAU1966AZ, and other questions --
Hi there, I'm Maurizio from Rome, Italy, I'm beginning to use Analog Devices boards but I'm a newby in such a world, therefore please forgive me if I'll not be too clear: moreover, english is not my m
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Issue with ExtSPIDelay on ADAU1452
Hello, We are using the development board for the ADAU1452 because we need to implement a big delay (we expect to be able to delay our sound up to 35 seconds). I am trying to use the functionality but
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ADAU145x datasheet ASRC group delay calculation
On page 81 of Rev.D of the ADAU145c datasheet there are calculations for the ASRC group delay : The same equations appear in the AD1895 datasheet, so surely they must be correct. In the first equation
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External Delay with ADAU1466
I have connected IS62WVS5128GBLL - 4MBit SRAM to ADAU1466. It used for block ExtDelay. Slave is 5, SPI Mode 3. It works well (only) with 13,5MHz. RAM size 524288 bytes. I have connected ExtDelay to ch
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External SPI Delay on ADAU1466
I am working on a project that requires a significant amount of delay. Altough all of the examples I've found concerning external SPI delay refer to the ADAU1452, I find that SigmaStudio shows the opt
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ADAU1466 With External Multi-Channel SPI Delay Issues/Questions
SETUP ADAU1466 Dev Board EEPROM swapped with 23LC1024 SPI RAM (1Mb) Sigma Studio v4.4 SPDIF In to SPDIF Out External SPI Configuration 48kHz Sampling The first output of the SPI delay always has a dif